| 4/2018 - 14 |
Design of Crosstalk Prevention Coding scheme based on Quintuplicated Manchester error correction method for Reliable on chip InterconnectsNARAYANASAMY, P.   , MUTHURATHINAM, S. , GOPALAKRISHNAN, S. |
Extra paper information in    |
| Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science |
Download PDF  (1,600 KB) | Citation | Downloads: 1,039 | Views: 3,514 |
Author keywords
codecs, error correction codes, system-on-chip, redundancy, reliability
References keywords
vlsi(18), systems(16), design(11), chip(11), crosstalk(9), very(8), scale(8), large(8), integration(8), error(8)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2018-11-30
Volume 18, Issue 4, Year 2018, On page(s): 113 - 120
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.04014
Web of Science Accession Number: 000451843400014
SCOPUS ID: 85058811531
Abstract
A low power Manchester based error-control code for on-chip interconnection-link has been proposed in this paper. It has a capacity to rectify nonuple errors of random and burst using standard N-Modular Redundancy (N-MR) error correction scheme. Manchester based Rectification of Single Error, Identification of Double Error(M-RSE-IDE) extended-Hamming code, and Quintuplication error correction scheme serves as the backbone for the proposed technique. Besides, both handle different tasks simultaneously. The former prevents the crosstalk of the interlinked-wire with the reduction in the coupling capacitance while the latter consumes less power by transiting data at the center of the bit. A new nonupler-decoding algorithm has put forward in the proposed Quintuplicated Manchester Error Correction (QMEC) to correct nine errors. Different analysis of reliability, area, power, delay and residual flit-error rate; interlink-swing voltage and interlink-power consumption of the designed QMEC code has been performed. The QMEC codec, when running with Manchester, counteracts nonuple errors with 25 percent of power reduction compared to QMEC without Manchester. QMEC not only outlined other existing error control codes by area and power but also reduced link-swing voltage and link power upto 91 percent and 85 percent respectively. |
| References | | | Cited By «-- Click to see who has cited this paper |
| [1] Chunjie Duan, V. H. C. Calle, and S. P. Khatri, "Efficient On-Chip Crosstalk Avoidance CODEC Design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 4, pp. 551-560, Apr. 2009. [CrossRef] [Web of Science Times Cited 65] [SCOPUS Times Cited 89] [2] S. Kumar, A. Jantsch, J.P. Soinonuplen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja and A. Hemani "A network on chip architecture and design methodology," in IEEE Computer Society Annual Symposium on VLSI, 2002, pp. 117-124. [CrossRef] [SCOPUS Times Cited 998] [3] S. R. Sridhara and N. R. Shanbhag, "Coding for system-on-chip networks: a unified framework," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 655-667, Jun. 2005. [CrossRef] [Web of Science Times Cited 119] [SCOPUS Times Cited 152] [4] C. Grecu, A. Ivanov, R. Saleh, and P. Pande, "NoC Interconnect Yield Improvement Using Crosspoint Redundancy," in 21st Internationl Symposium on Defect and Fault Tolerance in VLSI System, 2006, pp. 457-465. [CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 26] [5] T. Karnik and P. Hazucha, "Characterization of soft errors caused by single event upsets in CMOS processes," IEEE Transactions on Dependable and Secure Computing, vol. 1, no. 2, pp. 128-143, Apr. 2004. [CrossRef] [Web of Science Times Cited 342] [SCOPUS Times Cited 430] [6] A. Vittal, L. H. Chen, M. Marek-Sadowska, Kai-Ping Wang, and S. Yang, "Crosstalk in VLSI interconnections," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 12, pp. 1817-1824, Dec. 1999. [CrossRef] [Web of Science Times Cited 105] [SCOPUS Times Cited 146] [7] D. Sylvester and Chenming Wu, "Analytical modeling and characterization of deep-submicrometer interconnect," Proceedings of the IEEE, vol. 89, no. 5, pp. 634-664, May 2001. [CrossRef] [Web of Science Times Cited 119] [SCOPUS Times Cited 144] [8] A. V. Mezhiba and E. G. Friedman, "Scaling trends of on-chip power distribution noise," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 4, pp. 386-394, Apr. 2004. [CrossRef] [Web of Science Times Cited 55] [SCOPUS Times Cited 73] [9] E. Demircan, "Effects of Interconnect Process Variations on Signal Integrity," in 2006 IEEE International SOC Conference, 2006, pp. 281-284. [CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 15] [10] A. H. Ajami, K. Banerjee, and M. Pedram, "Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 849-861, Jun. 2005. [CrossRef] [Web of Science Times Cited 151] [SCOPUS Times Cited 199] [11] R. Khazaka and M. Nakhla, "Analysis of high-speed interconnects in the presence of electromagnetic interference," IEEE Transactions on Microwave Theory and Techniques, vol. 46, no. 7, pp. 940-947, Jul. 1998. [CrossRef] [Web of Science Times Cited 40] [SCOPUS Times Cited 46] [12] M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 3, no. 1, pp. 49-58, Mar. 1995. [CrossRef] [Web of Science Times Cited 558] [SCOPUS Times Cited 768] [13] T. Lehtonen, P. Liljeberg, and J. Plosila, "Online Reconfigurable Self-Timed Links for Fault Tolerant NoC," VLSI Design, vol. 2007, pp. 1-13, 2007. [CrossRef] [Web of Science Times Cited 40] [SCOPUS Times Cited 93] [14] D. Bertozzi, L. Benini, and G. De Micheli, "Error control schemes for on-chip communication links: the energy-reliability tradeoff," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 818-831, Jun. 2005. [CrossRef] [Web of Science Times Cited 40] [SCOPUS Times Cited 93] [15] M. R. Stan and W. P. Burleson, "Low-power encodings for global communication in CMOS VLSI," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, no. 4, pp. 444-455, Dec. 1997. [CrossRef] [Web of Science Times Cited 114] [SCOPUS Times Cited 142] [16] D. Rossi, C. Metra, A. K. Nieuwland, and A. Katoch, "Exploiting ECC redundancy to minimize crosstalk impact," IEEE Design and Test of Computers, vol. 22, no. 1, pp. 59-70, Jan. 2005. [CrossRef] [Web of Science Times Cited 51] [SCOPUS Times Cited 66] [17] K. N. Patel and I. L. Markov, "Error-correction and crosstalk avoidance in DSM busses," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1076-1080, Oct. 2004. . [CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 56] [18] A. Ganguly, P. P. Pande, and B. Belzer, "Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 11, pp. 1626-1639, Nov. 2009. [CrossRef] [Web of Science Times Cited 80] [SCOPUS Times Cited 104] [19] M. Maheswari and G. Seetharaman, "Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links," Microprocessors and Microsystems, vol. 37, no. 4-5, pp. 420-429, Jun. 2013. [CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 17] [20] Bo Fu and P. Ampadu, "On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 2042-2054, Sep. 2009. [CrossRef] [Web of Science Times Cited 52] [SCOPUS Times Cited 72] [21] Q. Yu and P. Ampadu, "Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment," in 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008, pp. 352-360. [CrossRef] [Web of Science Times Cited 24] [SCOPUS Times Cited 36] [22] D. Rossi, A. K. Nieuwland, A. Katoch, and C. Metra, "New ECC for Crosstalk Impact Minimization," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 340-348, Apr. 2005. [CrossRef] [Web of Science Times Cited 36] [SCOPUS Times Cited 46] [23] B. Fu and P. Ampadu, "Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects," in 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009, pp. 440-448. [CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 20] [24] P.-T. Huang and W. Hwang, "Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks," Journal of Electrical and Computer Engineering, vol. 2012, pp. 1-19, 2012. [CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 13] [25] V. Bobin, S. R. Whitaker, and G. K. Maki, "N -modular redundancy using the theory of error correcting codes," International Journal of Electronics, vol. 75, no. 6, pp. 1071-1081, Dec. 1993. [CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 2] [26] P. Balasubramanian, "ASIC-based design of NMR system health monitor for mission/safety-critical applications," SpringerPlus, vol. 5, no. 1, Dec. 2016. doi 10.1186/s40064-016-2249-7. [27] Y. Bentoutou, "A Real Time EDAC System for Applications Onboard Earth Observation Small Satellites," IEEE Transactions on Aerospace and Electronic Systems, vol. 48, no. 1, pp. 648-657, Jan. 2012. [CrossRef] [Web of Science Times Cited 42] [SCOPUS Times Cited 54] [28] Haryono, Jazi Eko Istiyanto, Agus Harjoko, Agfianto Eko Putra, "Five Modular Redundancy with Mitigation Technique to Recover the Error Module," Journal of Advanced studies in Computer Science and Engineering, vol 3, no. 2, pp. 15-20, 2014. [29] E. Abdulhay, V. Elamaran, N. Arunkumar, and V. Venkataraman, "Fault-tolerant medical imaging system with quintuple modular redundancy (QMR) configurations," Journal of Ambient Intelligence and Humanized Computing, Mar. 2018. [CrossRef] [SCOPUS Times Cited 32] [30] A. H. Elsayed, R. N. Tadros, M. Ghoneima, and Y. Ismail, "Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks," in 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, pp. 2752-2755. [CrossRef] [SCOPUS Times Cited 6] [31] N. Sowjith, K. S. Sandeep, M. Sumanth, and S. Agrawal, "Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs," in 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC),2016, pp. 1-5. [CrossRef] [SCOPUS Times Cited 8] [32] P. P. Sotiriadis and A. P. Chandrakasan, "A bus energy model for deep submicron technology," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 3, pp. 341-350, Jun. 2002. [CrossRef] [Web of Science Times Cited 100] [SCOPUS Times Cited 133] [33] B. Fu and P. Ampadu, "An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes," VLSI Design, vol. 2008, pp. 1-14, 2008. [CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 16] [34] Z. Shirmohammadi, F. Mozafari, and S.-G. Miremadi, "An efficient numerical-based crosstalk avoidance codec design for NoCs," Microprocessors and Microsystems, vol. 50, pp. 127-137, May 2017. [CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 16] [35] S. J. Gali and S. K. Terlapu, "On the Implementation of VLSI Architecture of FM0/Manchester Encoding and Differential Manchester Coding for Short-Range Communications," in Microelectronics, Electromagnetics and Telecommunications, vol. 471, 2018, pp. 551-558. [CrossRef] Web of Science® Citations for all references: 2,267 TCR SCOPUS® Citations for all references: 4,111 TCR Web of Science® Average Citations per reference: 63 ACR SCOPUS® Average Citations per reference: 114 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-19 00:32 in 222 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site. |
Copyright ©2001-2024
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
