2/2014 - 10 |
Pipelined Error-detecting Codes in FPGA TestingBREKHOV, O. , RATNIKOV, M. |
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Author keywords
field programmable gate arrays, design for testability, automatic testing, cyclic redundancy check codes, error correction codes
References keywords
fpga(13), testing(9), test(7), fpgas(6), fault(6), diagnosis(6), technology(5), design(5), systems(4), science(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2014-05-31
Volume 14, Issue 2, Year 2014, On page(s): 57 - 62
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.02010
Web of Science Accession Number: 000340868100010
SCOPUS ID: 84901841977
Abstract
This article approaches the solution of FPGA testing and research of characteristics at early development stages. The approach offers error-detection code based on universal test firmware. The performed test firmware based on CRC and Hamming codes detect single and multiple faults, and locate fault place (for Hamming code based test firmware). |
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[1] Low-power DSSS transmitter and its VLSI implementation, Jayasanthi, M., Kalaivani, R., Annals of Telecommunications, ISSN 0003-4347, Issue 7-8, Volume 76, 2021.
Digital Object Identifier: 10.1007/s12243-021-00837-z [CrossRef]
[2] Using pipelined control code generator as a reference system in FPGA’s selection as a hardware platform for fault-tolerance computing system, Brekhov, O, Ratnikov, M, Journal of Physics: Conference Series, ISSN 1742-6588, Issue 1, Volume 1925, 2021.
Digital Object Identifier: 10.1088/1742-6596/1925/1/012038 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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