4/2018 - 14 |
Design of Crosstalk Prevention Coding scheme based on Quintuplicated Manchester error correction method for Reliable on chip InterconnectsNARAYANASAMY, P. , MUTHURATHINAM, S. , GOPALAKRISHNAN, S. |
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Author keywords
codecs, error correction codes, system-on-chip, redundancy, reliability
References keywords
vlsi(18), systems(16), design(11), chip(11), crosstalk(9), very(8), scale(8), large(8), integration(8), error(8)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2018-11-30
Volume 18, Issue 4, Year 2018, On page(s): 113 - 120
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.04014
Web of Science Accession Number: 000451843400014
SCOPUS ID: 85058811531
Abstract
A low power Manchester based error-control code for on-chip interconnection-link has been proposed in this paper. It has a capacity to rectify nonuple errors of random and burst using standard N-Modular Redundancy (N-MR) error correction scheme. Manchester based Rectification of Single Error, Identification of Double Error(M-RSE-IDE) extended-Hamming code, and Quintuplication error correction scheme serves as the backbone for the proposed technique. Besides, both handle different tasks simultaneously. The former prevents the crosstalk of the interlinked-wire with the reduction in the coupling capacitance while the latter consumes less power by transiting data at the center of the bit. A new nonupler-decoding algorithm has put forward in the proposed Quintuplicated Manchester Error Correction (QMEC) to correct nine errors. Different analysis of reliability, area, power, delay and residual flit-error rate; interlink-swing voltage and interlink-power consumption of the designed QMEC code has been performed. The QMEC codec, when running with Manchester, counteracts nonuple errors with 25 percent of power reduction compared to QMEC without Manchester. QMEC not only outlined other existing error control codes by area and power but also reduced link-swing voltage and link power upto 91 percent and 85 percent respectively. |
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[1] VLSI Design of Low Power $8\times 4$ Barrel Shifter using 90 nm TG technology, Deepak Vudatha, Jaya Sai, Kota, Naveena, Gutha, Preethi, Sreeja, Baby, Rajeev, Sreenidhi Prabha, 2021 Fourth International Conference on Microelectronics, Signals & Systems (ICMSS), ISBN 978-1-6654-4885-7, 2021.
Digital Object Identifier: 10.1109/ICMSS53060.2021.9673648 [CrossRef]
[2] Low Power 90 nm 8 × 4 Pseudo NMOS Barrel Shifter Design, Vudatha, Jaya Sai Deepak, Rajeev, Sreenidhi Prabha, Sreeja, Baby, 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT), ISBN 978-1-6654-3272-6, 2021.
Digital Object Identifier: 10.1109/ICEECCOT52851.2021.9708048 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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