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An Automatic Instruction-Level Parallelization of Machine CodeMARINKOVIC, V.   , POPOVIC, M. , DJUKIC, M. |
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Author keywords
parallel architectures, parallel programming, multicore processing, assembly, processor scheduling
References keywords
parallel(13), code(10), parallelization(9), automatic(8), systems(7), programming(4), program(4), micro(4), data(4), architectures(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2018-02-28
Volume 18, Issue 1, Year 2018, On page(s): 27 - 36
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.01004
Web of Science Accession Number: 000426449500004
SCOPUS ID: 85043242372
Abstract
Prevailing multicores and novel manycores have made a great challenge of modern day - parallelization of embedded software that is still written as sequential. In this paper, automatic code parallelization is considered, focusing on developing a parallelization tool at the binary level as well as on the validation of this approach. The novel instruction-level parallelization algorithm for assembly code which uses the register names after SSA to find independent blocks of code and then to schedule independent blocks using METIS to achieve good load balance is developed. The sequential consistency is verified and the validation is done by measuring the program execution time on the target architecture. Great speedup, taken as the performance measure in the validation process, and optimal load balancing are achieved for multicore RISC processors with 2 to 16 cores (e.g. MIPS, MicroBlaze, etc.). In particular, for 16 cores, the average speedup is 7.92x, while in some cases it reaches 14x. An approach to automatic parallelization provided by this paper is useful to researchers and developers in the area of parallelization as the basis for further optimizations, as the back-end of a compiler, or as the code parallelization tool for an embedded system. |
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[1] A systematic review on Transpiler usage for Transaction-Oriented Applications, Bastidas, F. Andres, Perez, Maria, 2018 IEEE Third Ecuador Technical Chapters Meeting (ETCM), ISBN 978-1-5386-6657-9, 2018.
Digital Object Identifier: 10.1109/ETCM.2018.8580312 [CrossRef]
[2] NeurOMP: Paralelização automática de código utilizando Aprendizagem por Reforço, Saffran, João, Rocha, Rodrigo Caetano, Góes, Luís Fabrício, Anais do XXI Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD 2020), ISBN , 2020.
Digital Object Identifier: 10.5753/wscad.2020.14060 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
