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Embedded Processor Oriented Compiler InfrastructureDJUKIC, M.   , POPOVIC, M. , CETIC, N. , POVAZAN, I. |
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Author keywords
digital signal processors, embedded software, fixed-point arithmetic, software tools
References keywords
embedded(12), systems(10), compiler(10), code(10), optimization(7), design(7), compilers(6), processors(5), generation(5), sigplan(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2014-08-31
Volume 14, Issue 3, Year 2014, On page(s): 123 - 130
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.03016
Web of Science Accession Number: 000340869800016
SCOPUS ID: 84907337455
Abstract
In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture. |
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| [1] J. A. Fisher, P. Faraboschi, C. Young. Embedded computing: A WLIW approach to architecture, compilers, and tools. pp. 9-16, Morgan Kaufmann, 2005.
[2] L. H. Hamel, "Industrial strength compiler construction with equations", ACM SIGPLAN Notices, Volume 27, Issue 8, pp. 43-50, 1992, [CrossRef] [SCOPUS Times Cited 2] [3] Cirrus Logic 32-bit DSP Assembly Programmer's Guide, Cirrus Logic Inc., 2013. [Online] [4] JTC1/SC22/WG14, Programming languages - C - Extensions to support embedded processors, Technical report, ISO/IEC, 2006. [5] R. Leupers, "Code generation for embedded processors", in Proc. 13th International Symposium on System Synthesis (ISSS'00), Madrid, 2000, [CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 35] [6] R. Leupers, "Compiler design issues for embedded processors", IEEE Design & Test of Computers, Volume 19, Issue 4, pp. 51-58, 2002, [CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 31] [7] M. Wolfe, "How compilers and tools differ for embedded systems", Proc. 2005 international conference on Compilers, architectures and synthesis for embedded systems, New York, 2005. [CrossRef] [SCOPUS Times Cited 12] [8] G. Fursin, O. Temam, "Collective optimization: a practical collaborative approach", ACM Transactions on Architecture and Code Optimization, Volume 7, No. 4, Article 20, 2010, [CrossRef] [Web of Science Times Cited 25] [SCOPUS Times Cited 34] [9] D. R. White, A. Arcuri, J. A. Clark, "Evolutionary Improvement of Programs", IEEE Transactions on Evolutionary Computation, Vol. 15, No. 4, pp. 515-538, 2011, [CrossRef] [Web of Science Times Cited 79] [SCOPUS Times Cited 114] [10] P. A. Kulkarni, D. B. Whalley, G. S. Tyson, J. W. Davidson, "Practical Exhaustive Optimization Phase Order Exploration and Evaluation", ACM Transactions on Architecture and Code Optimization, Vol. 6, Issue 1, Article 1, 2009, [CrossRef] [Web of Science Times Cited 39] [SCOPUS Times Cited 45] [11] S. Bashford, R. Laupers, "Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths", Design Automation for Embedded Systems, Volume 4, Issue 2-3, pp. 119-165, 1999, [CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 20] [12] S. Rajagopalan, S. P. Rajan, S. Malik, S. Rigo, G. Araujo, K. Takayama, "A retargetable VLIW compiler framework for DSPs with instruction-level parallelism", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, Issue 11, pp. 1319-1328, 2001, [CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 14] [13] M. Eriksson, C. Kessler, "Integrated Code Generation for Loops", ACM Transactions on Embedded Computing Systems, Vol. 11S, Issue 1, No. 19, 2012, [CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 14] [14] G. W. Grewal, C. T. Wilson, "Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)", Proceedings 34th ACM/IEEE International Symposium on Microarchitecture, pp. 192-202, 2001, [CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 7] [15] Y. Choi, T. Kim, "Address assignment in DSP code generation - an integrated approach", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, Issue 8, pp. 976-984, 2003, [CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 6] [16] G. Talavera, M. Jayapala, J. Carrabina, F. Catthoor, "Address Generation Optimization for Embedded High-Performance Processors: A Survey", Journal of Signal Processing Systems, Vol. 53, Issue 3, pp. 271-284, 2008, [CrossRef] [Web of Science Times Cited 18] [SCOPUS Times Cited 24] [17] V. Bertin, J. Daveau, P. Guillaume, T. Lepley, D. Pilat, C. Richard, M. Santana, T. Thery, "FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors", Lecture Notes in Computer Science Volume 2491, pp. 382-398, 2002. [CrossRef] [SCOPUS Times Cited 6] [18] D. Ebner, F. Brandner, B. Scholz, A. Krall, P. Wiedermann, A. Kadlec, "Generalized instruction selection using SSA-graphs", ACM SIGPLAN Notices - LCTES '08, Vol. 43, Issue 7, pp. 31-40, 2008, [CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 5] [19] G. Chen, M. Kandemir, "Optimizing embedded applications using programmer-inserted hints", Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific, Vol. 1, pp. 157-160, 2005, [CrossRef] [20] M. Deilmann, A Guide to Vectorization with Intel C++ Compilers, Intel Corporation, pp. 20-21, 2012. [Online] [21] A. W. Appel. Modern compiler implementation in C, Second edition, pp. 219-240, Cambridge University Press, 2004. [22] C. W. Fraser, R. R. Henry, T. A. Proebsting, "BURG - Fast optimal instruction selection and tree parsing", ACM SIGPLAN Notices, Volume 27, Issue 4, pp. 68-76, 1992, [CrossRef] [SCOPUS Times Cited 96] [23] C. W. Fraser, D. R. Hanson, T. A. Proebsting, "Engineering a simple, efficient code generator generator", ACM Letters on Programming Languages and Systems, Volume 1, Issue 3, pp. 213-226, 1992, [CrossRef] [SCOPUS Times Cited 144] [24] K. D. Cooper, L. Torczon. Engineering a compiler, pp. 595-604, 569-579 Morgan Kaufmann, 2004. [25] A. V. Aho, M. S. Lam, R. Sethi, J. D. Ullman, Compilers: principles, techniques, & tools, Second edition, pp. 549-553, Addison-Wesley, 2007. [26] T. A. Johnson, S. I. Lee, L. Fei, A. Basumallik, G. Upadhyaya, R. Eigenmann, S. P. Midkiff, "Experiences in Using Cetus for Source-to-Source Transformations", Languages and Compilers for High Performance Computing, pp. 1-14, 2005, [CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 11] [27] M. Djukic, N. Cetic, R. Obradovic, M. Popovic, "An approach to instruction set compiled simulator development based on a target processor C compiler back-end design", Innovations in Systems and Software Engineering: Volume 9, Issue 3, pp. 135-145, 2013, [CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1] [28] D. Guilan, Z. Suqing, T. Jinlan, J. Weidu, "A Study of Compiler Techniques for Multiple Targets in Compiler Infrastructures", ACM SIGPLAN Notices, Volume 37, Issue 6, pp. 45-51, 2002, [CrossRef] [29] A. Nicolau, R. Potasman, "Realistic scheduling: compaction for pipelined architectures", MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, Orlando, pp. 69-79, 1990, [CrossRef] [30] P. Lokuciejewski, D. Cordes, H. Falk, P. Marwedel, "A Fast and Precise Static Loop Analysis Based on Abstract Interpretation, Program Slicing and Polytope Models", Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO '09), Washington, pp. 136-146, 2009, [CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 62] [31] V. Zivojnovic, J.M. Velarde, C. Schlager, H. Meyer, "DSP-stone: A DSP-oriented benchmarking methodology", Proceedings of International Conference on Signal Processing Applications and Technology, 1994, pp. 715-720. [32] I. Povaan, M. Popovic, M. Dukic, and M. Krnjetin, "Measuring the quality characteristics of an assembly code on embedded platforms", Telfor Journal, Volume 4, No. 1, 2012, [CrossRef] [SCOPUS Times Cited 2] [33] H. M. Kienle, J. Kraft, Thomas Nolte, "System-specific static code analyses: a case study in the complex embedded systems domain", Software Quality Journal, Vol. 20, Issue 2, pp. 337-367, 2012, [CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 7] [34] A. Barleanu, V. Baitoiu, A. Stan, "Digital filter optimization for C language," Advances in Electrical and Computer Engineering, Vol. 11, no. 3, pp. 111-114, 2011, [CrossRef] [Full Text] [Web of Science Times Cited 4] [SCOPUS Times Cited 4] Web of Science® Citations for all references: 274 TCR SCOPUS® Citations for all references: 696 TCR Web of Science® Average Citations per reference: 8 ACR SCOPUS® Average Citations per reference: 20 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-04-12 16:39 in 195 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
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Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
