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JCR Impact Factor: 0.700
JCR 5-Year IF: 0.700
SCOPUS CiteScore: 1.8
Issues per year: 4
Current issue: Nov 2024
Next issue: Feb 2025
Avg review time: 56 days
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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  1/2017 - 11

 HIGH-IMPACT PAPER 

A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure

CHIPER, D. F. See more information about CHIPER, D. F. on SCOPUS See more information about CHIPER, D. F. on IEEExplore See more information about CHIPER, D. F. on Web of Science, CRACAN, A. See more information about  CRACAN, A. on SCOPUS See more information about  CRACAN, A. on SCOPUS See more information about CRACAN, A. on Web of Science, BURDIA, D. See more information about BURDIA, D. on SCOPUS See more information about BURDIA, D. on SCOPUS See more information about BURDIA, D. on Web of Science
 
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Download PDF pdficon (1,332 KB) | Citation | Downloads: 1,309 | Views: 1,008

Author keywords
discrete transforms, digital integrated circuits, field programmable gate arrays, large scale integration, systolic arrays

References keywords
systems(17), circuits(15), processing(14), signal(13), systolic(12), discrete(12), transform(10), efficient(10), algorithm(10), vlsi(9)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 75 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01011
Web of Science Accession Number: 000396335900011
SCOPUS ID: 85014197433

Abstract
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In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a new efficient VLSI algorithm based on a regular and modular computational structure called pseudo-band correlation structure. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low hardware complexity and low I/O cost. A highly efficient VLSI chip can be obtained characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N, a good topology with modular, regular and local connections.


References | Cited By

Cited-By Clarivate Web of Science

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Cited-By SCOPUS

SCOPUS® Times Cited: 14
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Cited-By CrossRef

[1] RETRACTED ARTICLE: Multimodal transport path optimization model and algorithm considering carbon emission multitask, Li, HuiFang, Su, Luan, The Journal of Supercomputing, ISSN 0920-8542, Issue 12, Volume 76, 2020.
Digital Object Identifier: 10.1007/s11227-019-03103-1
[CrossRef]

[2] Low-power DSSS transmitter and its VLSI implementation, Jayasanthi, M., Kalaivani, R., Annals of Telecommunications, ISSN 0003-4347, Issue 7-8, Volume 76, 2021.
Digital Object Identifier: 10.1007/s12243-021-00837-z
[CrossRef]

[3] An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach, Chiper, Doru Florin, Cracan, Arcadie, Andries, Vasilica-Daniela, Electronics, ISSN 2079-9292, Issue 15, Volume 11, 2022.
Digital Object Identifier: 10.3390/electronics11152416
[CrossRef]

[4] An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead, Chiper, Doru Florin, Cracan, Arcadie, Applied Sciences, ISSN 2076-3417, Issue 12, Volume 13, 2023.
Digital Object Identifier: 10.3390/app13126927
[CrossRef]

[5] A New VLSI Algorithm for a VLSI Implementation of MDST using Obfuscation Technique, Chiper, Doru Florin, Cracan, Arcadie, 2022 International Symposium on Electronics and Telecommunications (ISETC), ISBN 978-1-6654-5150-5, 2022.
Digital Object Identifier: 10.1109/ISETC56213.2022.10009927
[CrossRef]

[6] A Low Complexity Algorithm for the VLSI Implementation of DST Based on Band-correlation Structures, Chiper, Doru Florin, Cotorobai, Laura-Teodora, 2019 International Symposium on Signals, Circuits and Systems (ISSCS), ISBN 978-1-7281-3896-1, 2019.
Digital Object Identifier: 10.1109/ISSCS.2019.8801792
[CrossRef]

[7] A New Integer Algorithm for a VLSI Implementation of DCT Using Obfuscation Technique, Chiper, Doru Florin, Cracan, Arcadie, 2022 14th International Conference on Communications (COMM), ISBN 978-1-6654-9485-4, 2022.
Digital Object Identifier: 10.1109/COMM54429.2022.9817258
[CrossRef]

[8] A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations, CHIPER, Doru Florin, COTOROBAI, Laura Teodora, 2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), ISBN 978-1-5386-4901-5, 2018.
Digital Object Identifier: 10.1109/ECAI.2018.8679099
[CrossRef]

[9] A Novel VLSI Algorithm for a Low Complexity VLSI Implementation of DCT Based on Pseudo Circular Correlation Structures, Chiper, Doru Florin, Cotorobai, Laura Teodora, 2020 International Symposium on Electronics and Telecommunications (ISETC), ISBN 978-1-7281-8921-5, 2020.
Digital Object Identifier: 10.1109/ISETC50328.2020.9301043
[CrossRef]

[10] An Efficient Algorithm for the VLSI Implementation of the Inverse DST Based on Quasi-Band Correlation Structures, Chiper, Doru-Florin, Cracan, Arcadie, 2021 International Symposium on Signals, Circuits and Systems (ISSCS), ISBN 978-1-6654-4942-7, 2021.
Digital Object Identifier: 10.1109/ISSCS52333.2021.9497379
[CrossRef]

[11] An Efficient Algorithm for the VLSI Implementation of Inverse DCT Based on Quasi-Circular Correlation Structures, Chiper, D. F., Cotorobai, L.-T., 2021 15th International Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS), ISBN 978-1-6654-4442-2, 2021.
Digital Object Identifier: 10.1109/TELSIKS52058.2021.9606373
[CrossRef]

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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