2/2004 - 15 |
Building a SOC Architecture in an FPGAMarius CERLINCA, Adrian GRAUR |
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Author keywords
FPGA, SoC, Ethernet, FLASH write, SRAM, synthesis, debug, processor, core
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About this article
Date of Publication: 2004-04-02
Volume 4, Issue 2, Year 2004, On page(s): 77 - 81
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: Not assigned
Abstract FPGA's can be programmed to implement almost any digital circuit beginning with the simplest ones up to new microcontrollers and processors. One of the last fields of interest in developing with FPGA circuits is general SoC (System On a Chip) architecture. The reasons of the success this type of system has are multiple: unique functionalities and features, lower final costs, reduced number of components, high integration and higher product security. SoC's can be divided in two distinct categories: commercial and freeware. From commercial SoC's we can mention the TriCore family produced by Infineon Gmbh with the following peripherals implemented: Ethernet controller, USB 1.1 module, 1 MultiCAN module with 4 CAN nodes, 3 asynchronous/synchronous serial channels, 2 high speed synchronous serial channels, inter IC (IIC) serial module and 2 high speed Micro Link interfaces. From the freeware SoC's category we can mention: Wishbone System6800/01, System09 or C-NIT processor. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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