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Instruction-level Real-time Secure Processor Using an Error Correction CodeYOON, S. M.   , LEE, S. W. , PARK, J. K. , KIM, J. T. |
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Author keywords
secure processor, security, instruction, correlation, chain
References keywords
security(5), systems(4), secure(4), execution(4), efficient(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2015-08-31
Volume 15, Issue 3, Year 2015, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.03002
Web of Science Accession Number: 000360171500002
SCOPUS ID: 84940746882
Abstract
In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area. |
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| [1] M. L. Pollar, F. Martinelli and D. Sgandurra, "A Survey on Security for Mobile Devices," IEEE Comm. Surveys and Tutorials, Vol.15, No.1, pp.446-471, 2013. [CrossRef] [Web of Science Times Cited 282] [SCOPUS Times Cited 403] [2] K. Nikita, "Security and Privacy in Biomedical Telemetry: Mobile Health Platform for Secure Information Exchange," Wiley-IEEE Press eBook Chapters, 2014. [CrossRef] [SCOPUS Times Cited 7] [3] S. Ravi, A. Raghunathan, P. Kocher, and S. Hattangady, "Security in Embedded Systems: Design Challenges," ACM Trans. on Embedded Computing Systems, Vol. 3, pp. 461-491, 2004. [CrossRef] [SCOPUS Times Cited 385] [4] A. Murat Fiskiran, Ruby B. Lee "Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution" ICCD, 2004. [CrossRef] [Web of Science Times Cited 36] [SCOPUS Times Cited 45] [5] T. Maude and D. Maude, "Hardware Protection Against Software Piracy", Communications of the ACM, vol. 27, no. 9, pp.950-959, 1984. [CrossRef] [Web of Science Times Cited 22] [SCOPUS Times Cited 29] [6] D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. Mitchell and M. Horowitz, "Architectural Support for Copy and Tamper Resistant Software", Proc. of ASPLOS, pp. 168-177, 2000. [CrossRef] [7] V. Kiriansky, D. Bruening, and S. Amarasinghe, "Secure Execution via Program Sheperding," Proc. of 11th USENIX Security Symp., pp.191-206, 2002. [8] D. L. Detlefs, K. Leino, G. Nelson, and J. Saxe, "Extended static checking," Tech. rep., Systems Research Center, Compaq Inc., pp.1-44, 1998. [9] S. W. Lee and J. T. Kim, "Instruction Level Tampering Detection Technique using Error Detection Code for Embedded Systems," Proc. of ICCMSE, Vol. 1, pp.1-4. 2005. [10] W. Arbaugh, D. Farber, and J. Smith. "A secure and reliable bootstrap architecture" Proc. of IEEE Symp. on Security, pp.65-71, 1997. [CrossRef] [Web of Science Times Cited 180] [11] G. E. Suh, D. Clarke, B. Gassend, M. V. Dijk, S. Devadas, "Efficient Memory Integrity Verification and Encryption for Secure Processors", Proc. of IEEE/ACM Int'l. Sym. on MICRO, pp. 339-350, 2003. [CrossRef] [SCOPUS Times Cited 205] [12] J. P. McGregor, D. K. Karig, Z.Shi, and Ruby B. Lee, "A Processor Architecture Defense against Buffer Overflow Attacks", Proc. of IEEE Int'l. Conf. ITRE, pp. 243-250, 2003. [CrossRef] [Web of Science Times Cited 36] [SCOPUS Times Cited 51] [13] B. Gassend, G. E. Suh, D. Clarke, M. V. Dijk, and S. Devadas, "Caches and Hash Trees for Efficient Memory Integrity Verification", Proc. of Int'l Symp. on HPCA, pp.295-306, 2003. [CrossRef] [Web of Science Times Cited 121] [SCOPUS Times Cited 224] [14] S. T. J. Fenn, M. Benaissa, and D. Taylor, "Bit-serial Berlekamp-like multipliers for GF(2m)," Electronics Letters, Vol. 31, 1995, pp. 1893-1894, [CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 10] [15] I. S. Reed and X. Chen, "Error-Control Coding for Data Network," Kluwer Academic Publishers, 1999. [16] S. W. Lee, J.T. Kim and J-S. Cha, "Implementation of Adaptive Reed-Solomon Decoder for Context-Aware Mobile Computing Device," LNCS, Vol. 3681, 2005. [CrossRef] [SCOPUS Times Cited 2] [17] F-X. Standaert, G. Rouvroy, J-J. Quisquater, and J-D. Legat, "Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs," LNCS, vol.2779, pp. 334-350, 2003. [CrossRef] [18] G. P. Saggese, A. Mazzeo, N. Mazzocca, and A.G.M. Strollo, "An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm," LNCS, vol.2778, pp.292-302, 2003. [CrossRef] [SCOPUS Times Cited 87] [19] S-S. Wang, and W-S. Ni, "An Efficient FPGA Implementation of Advanced Encryption Standard Algorithm," Proc. of ISCAS 2004, Vol. 2, pp. 597-600, 2004. [CrossRef] [SCOPUS Times Cited 52] [20] W. Shi, H-H. S. Lee, C. Lu, and M. Ghosh. "Towards the Issues in Architectural Support for Protection of Software Execution." Proc. of ASPLOS, pp.1-10, 2004. [CrossRef] Web of Science® Citations for all references: 683 TCR SCOPUS® Citations for all references: 1,500 TCR Web of Science® Average Citations per reference: 33 ACR SCOPUS® Average Citations per reference: 71 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-14 11:56 in 111 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
