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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2025-Jun-19
Clarivate Analytics published the InCites Journal Citations Report for 2024. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.700 (0.600 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.600.

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SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

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  3/2018 - 2

High-Level Crosstalk Model in N-Coupled Through-Silicon Vias (TSVs)

LEE, H. See more information about LEE, H. on SCOPUS See more information about LEE, H. on IEEExplore See more information about LEE, H. on Web of Science, PARK, J. K. See more information about  PARK, J. K. on SCOPUS See more information about  PARK, J. K. on SCOPUS See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
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Download PDF pdficon (1,593 KB) | Citation | Downloads: 1,284 | Views: 3,388

Author keywords
integrated circuit reliability, SPICE, crosstalk, interconnect, through-silicon via

References keywords
design(13), systems(7), silicon(6), integration(6), integrated(6), circuits(6), chip(6), vias(5), technology(5), modeling(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-08-31
Volume 18, Issue 3, Year 2018, On page(s): 9 - 14
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.03002
Web of Science Accession Number: 000442420900002
SCOPUS ID: 85052155428

Abstract
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This paper proposes a regression noise model that can cover the noise effect from N-coupled TSVs based on SPICE simulation and reliability analysis flow for high-level simulation using a regression model. Regression analysis is adopted to develop a simple noise model with a single parameter and use the superposition theorem to extend the number of TSV lines that produce the noise. The proposed regression model has over 99 percent accuracy with SPICE in the given parameter range. For the N-coupled TSV wire, the regression noise model has over 96 percent accuracy. This paper choose the transaction level simulation for the high-level proposed analysis flow to calculate the single bit error rate of over 100 billion transaction data in a few minutes. Our simulation result shows the effect of the N-coupled TSV crosstalk glitch noise on the single bit error rate when the probability function type of the manufacturing noise is considered.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [SCOPUS Times Cited 41]


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References Weight

Web of Science® Citations for all references: 2,458 TCR
SCOPUS® Citations for all references: 3,546 TCR

Web of Science® Average Citations per reference: 98 ACR
SCOPUS® Average Citations per reference: 142 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2025-06-01 11:42 in 160 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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