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Exploring FPGA Logic Block Architecture for Reduced Configuration MemoryHUSSAIN, F.   , IQBAL, M. M. , PARVEZ, H. , RASHID, M. |
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Author keywords
clustering algorithms, field programmable gate arrays, programmable logic arrays, reconfigurable architectures, reconfigurable logic
References keywords
fpga(17), systems(12), logic(12), parvez(10), application(10), specific(8), reconfigurable(8), fpgas(8), computing(8), programmable(7)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2022-08-31
Volume 22, Issue 3, Year 2022, On page(s): 15 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2022.03002
Web of Science Accession Number: 000861021000002
SCOPUS ID: 85137679653
Abstract
The reduction of reconfiguration delay, during the partial dynamic reconfiguration of FPGAs, is important. In this context, the bitstream compression technique is one of the widely used techniques. These compression techniques only minimize the size of the bitstream whereas the actual configuration memory size on FPGA remains the same, which consumes area as well as power. Therefore, alternative techniques are required to decrease area and power consumption along with the reconfiguration delays. This work optimizes the configuration memory requirements in the Configurable Logic Block (CLB) of FPGA with SRAM table sharing technique. The SRAM table of a Look-Up-Table (LUT) is shared with one or more LUTs in the same CLB by employing Negation-Permutation-Negation (NPN) classification. Furthermore, the relevant CAD tools are modified to explore the heterogeneous degree of SRAM table sharing within a CLB. For validation, extensive explorations are performed on the 20 largest MCNC benchmark circuits. It has been found that the configuration memory requirements of LUTs are reduced by 30% while retaining the same area, occupancy, and delay. Moreover, it can be further reduced by 50% provided that the FPGA occupancy is allowed to increase by only 15% while retaining the same delay. |
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| [1] T. S. S. Phani, A. Arumalla, M. D. Prakash, "Partial dynamic reconfiguration framework for FPGA: A survey with concepts, constraints and trends," Materials Today: Proceedings 2021. [CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 3] [2] A. Podobas, K. Sano, S. Matsuoka, "A survey on coarse grained reconfigurable architectures from a performance perspective," IEEE Access 8 (2020) 146719-146743. [CrossRef] [Web of Science Times Cited 70] [SCOPUS Times Cited 80] [3] K. E. Murray, J. Luu, M.J.P. Walker, C. McCullough, S. Wang, S. Huda, B. Yan, C. Chiasson, K.B. Kent, J. Anderson, J. Rose, V. Betz, "Optimizing FPGA logic block architectures for arithmetic," IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6) (2020) 1378-1391. [CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 10] [4] M. Eldafrawy, A. Boutros, S. Yazdanshenas, V. Betz, "FPGA logic block architectures for effcient deep learning inference," ACM Trans. Reconfigurable Technol. Syst. 13 (3). [CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 20] [5] A. Boutros, M. Eldafrawy, S. Yazdanshenas, V. Betz, "Math doesn't have to be hard: Logic block architectures to enhance low-precision multiply-accumulate on FPGAs," in: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '19, Association for Computing Machinery, New York, NY, USA, 2019, p. 94-103. [CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 15] [6] A. Valanarasi, S. SithiShameem Fathima, C. Priya, B. Babu Mohan, J. Preethipilomina, M. Jannath Juvairiya, "Optimizing FPGA logic block architectures for self-repairing hardened arithmetic," Materials Today: Proceedings. [CrossRef] [SCOPUS Times Cited 1] [7] H. Chen, H. Yang, W. Song, Z. Lu, Y. Fu, L. Li, Z. Yu, "Symmetric-mapping LUT-based method and architecture for computing XY-like functions," IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3) (2021) 1231-1244. [CrossRef] [Web of Science Times Cited 15] [SCOPUS Times Cited 20] [8] K. Vipin, S.A. Fahmy, "FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications," ACM Comput. Surv. 51 (4). [CrossRef] [Web of Science Times Cited 122] [SCOPUS Times Cited 154] [9] J. S. Meena, S. M. Sze, U. Chand, T. Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale Research Letters 9 (526) (2014) 118:1-118:39. [CrossRef] [Web of Science Times Cited 551] [SCOPUS Times Cited 614] [10] R. T. I. Kuon, J. Rose, "FPGA architecture: Survey and challenges," Foundations and Trends in Electronic Design Automation 2.2 (2008) 135-253. [CrossRef] [Web of Science Times Cited 283] [SCOPUS Times Cited 369] [11] X. Zhang, C. Paerson, Y. Liu, C. Yang, C. J. Xue, J. Hu, "Low overhead online data flow tracking for intermittently powered non-volatile FPGAs," ACM Journal on Emerging Technologies in Computing Systems. [CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 6] [12] A. Chen, "A review of emerging non-volatile memory (NVM) technologies and applications," Solid-State Electronics 125 (2016) 25-38. [CrossRef] [Web of Science Times Cited 407] [SCOPUS Times Cited 465] [13] I. Hariharan, M. Kannan, "Efficient use of on-chip memories and scheduling techniques to eliminate the reconfiguration overheads in reconfigurable systems," Journal of Circuits, Systems and Computers 28 (14) (2019) 1950246. [CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 2] [14] E. Ahmed, J. Rose, "The effect of LUT and cluster size on deep submicron FPGA performance and density," Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 2004, pp. 288-298, [CrossRef] [Web of Science Times Cited 188] [SCOPUS Times Cited 276] [15] W. Feng, J. Greene, A. Mishchenko, "Improving FPGA performance with a S44 LUT structure," in: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '18, Association for Computing Machinery, New York, NY, USA, 2018, p. 61-66. [CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 27] [16] Y. Okamoto, Y. Ichinomiya, M. Amagasaki, M. Iida and T. Sueyoshi, "COGRE: A configuration memory reduced reconfigurable logic cell architecture for area minimization," 2010 International Conference on Field Programmable Logic and Applications, 2010, pp. 304-309. [CrossRef] [SCOPUS Times Cited 20] [17] P. A. Hadi, B. Hind, N. David, P. Ienne, "Rethinking FPGAs: Elude the flexibility excess of LUTs with and-inverter cones," in International Symposium On Field Programmable Gate Arrays (2012) 119-128. [CrossRef] [SCOPUS Times Cited 29] [18] Q. Zhao, K. Yanagida, M. Amagasaki, M. Iida, M. Kuga, T. Sueyoshi, "A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory," in Field Programmable Logic and Applications (FPL), 2014. [CrossRef] [SCOPUS Times Cited 5] [19] J. Meyer, F. Kocan, "Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs," vol. 15, IEEE Transactions on Very Large Scale Integration Systems (VLSI), 2007. [CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 17] [20] A. Asghar, M. M. Iqbal, W. Ahmed, M. Ali, H. Parvez, and M. Rashid, "Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs," in International Conference on Field Programmable Technology (ICFPT). [CrossRef] [SCOPUS Times Cited 7] [21] A. Asghar, M. M. Iqbal, W. Ahmed, M. Ali, H. Parvez, M. Rashid, "Exploring shared SRAM tables in FPGAs for larger LUTs and higher degree of sharing," International Journal of Reconfigurable Computing 2017. [CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 5] [22] A. Asghar, M. M. Iqbal, W. Ahmed, M. Ali, H. Parvez, M. Rashid, "Logic algebra for exploiting shared SRAM-table based FPGAs for large LUT inputs," 2017 First International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT), IEEE. [CrossRef] [SCOPUS Times Cited 3] [23] M. M. Iqbal, H. Parvez, F. Hussain, M. Rashid, "An application specific reconfigurable architecture with reduced area and static memory cells," Journal of Circuits, Systems and Computers 30 (4). [CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 2] [24] H. Parvez, and M. Habib, "ASIF: Application specific inflexible FPGA," Application-Specific Mesh-based Heterogeneous FPGA Architectures. Springer, New York, NY, 2011, pp 77-101. [CrossRef] [25] U. Farooq, H. Parvez, H. Mehrez, and Z. Marrakchi, "A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA," In Microprocessors and Microsystems, (2012). 36(8), pp 588-605. [CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 10] [26] H. Parvez, Z. Marrakchi, A. Kilic, and H. Mehrez, "Application-specific FPGA using heterogeneous logic blocks," ACM Transactions on Reconfigurable Technology and Systems (TRETS), (2011) 4(3), pp 1-14. [CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 7] [27] U. Farooq, H. Parvez, H. Mehrez, and Z. Marrakchi, "Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA," Microelectronics Journal, 2013, 44(12), pp 1052-1062. [CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1] [28] M. M. Iqbal, H. Parvez, and M. Rashid, "Multi-Circuit": Automatic generation of an application specific configurable core for known set of application circuits," Journal of Circuits, Systems and Computers, 2016, 25(09), 1650102. [CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 5] [29] M. M. Iqbal, H. Parvez, "Optimizing routing network of shared hardware design for multiple application circuits," In 2017 First International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT) (pp. 1-4). IEEE. [CrossRef] [SCOPUS Times Cited 1] [30] K. E. Murray, O. Petelin, S. Zhong, J. M. Wang, M. Eldafrawy, J. P. Legault, E. Sha, A. G. Graham, J. Wu, M. J. P. Walker, H. Zeng, P. Patros, J. Luu, K. B. Kent, V. Betz, "VTR 8: High performance CAD and customizable FPGA architecture modelling," ACM Transactions on Reconfigurable Technology and SystemsVolume 13 Issue 2 June 2020 Article No.: 9 pp 1-55. [CrossRef] [Web of Science Times Cited 137] [SCOPUS Times Cited 185] [31] K. S. McElvain, "Benchmark Set: Version 4.0," MCNC International Workshop on Logic Synthesis, 1993 [32] P. Jamieson, K. B. Kent, F. Gharibian, L. Shannon, "Odin II - An open-source verilog HDL synthesis tool for CAD research," in: 2010 18th IEEE Annual International Symposium on Field Programmable Custom Computing Machines, 2010, pp. 149-156. Berkeley Logic Synthesis and Verification1 Group, ABC: A System for Sequential Synthesis and Verification. [CrossRef] [Web of Science Times Cited 94] [SCOPUS Times Cited 134] [33] R. Brayton, A. Mishchenko, "ABC: An academic industrial-strength verification tool," In: Touili T., Cook B., Jackson P. (eds) Computer Aided Verification. CAV 2010. Lecture Notes in Computer Science, vol 6174. Springer, Berlin, Heidelberg. [CrossRef] [SCOPUS Times Cited 626] [34] V. P. Correia, A. I. Reis, Classifying n-input Boolean functions, VII Workshop Iberchip. [35] J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, et al., "VTR 7.0: Next generation architecture and CAD system for FPGAs," vol. 7, ACM Transactions on Reconfgurable Technology and Systems (TRETS), 2014. [CrossRef] [Web of Science Times Cited 225] [SCOPUS Times Cited 311] Web of Science® Citations for all references: 2,196 TCR SCOPUS® Citations for all references: 3,430 TCR Web of Science® Average Citations per reference: 61 ACR SCOPUS® Average Citations per reference: 95 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-20 13:02 in 233 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
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Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
