2/2011 - 6 |
Improving the Delay of Residue-to-Binary Converter for a Four-Moduli SetMOLAHOSSEINI, A. S. |
Extra paper information in |
Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science |
Download PDF (619 KB) | Citation | Downloads: 1,293 | Views: 4,825 |
Author keywords
Residue Number System (RNS), residue-to-binary converter, digital circuits, computer architecture, high-speed computer arithmetic
References keywords
systems(20), residue(19), moduli(16), binary(15), circuits(14), converter(13), efficient(8), converters(7), design(6), vlsi(5)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2011-05-30
Volume 11, Issue 2, Year 2011, On page(s): 37 - 42
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2011.02006
Web of Science Accession Number: 000293840500006
SCOPUS ID: 79958809141
Abstract
The residue number system (RNS) is an unconventional number system which can be used to achieve high-performance hardware implementations of special-purpose computation systems such as digital signal processors. The moduli set {2n-1, 2n, 2n+1, 22n+1-1} has been recently suggested for RNS to provide large dynamic range with low-complexity, and enhancing the speed of internal RNS arithmetic circuits. But, the residue-to-binary converter of this moduli set relies on high conversion delay. In this paper, a new residue-to-binary converter for the moduli set {2n-1, 2n, 2n+1, 22n+1-1} using an adder-based implementation of new Chinese remainder theorem-1 (CRT-I) is presented. The proposed converter is considerably faster than the original residue-to-binary converter of the moduli set {2n-1, 2n, 2n+1, 22n+1-1}; resulting in decreasing the total delay of the RNS system. |
References | | | Cited By «-- Click to see who has cited this paper |
[1] B. Parhami. Computer Arithmetic: Algorithms and Hardware Design. Oxford University Press, 2000.
[2] A. Omondi and B. Premkumar. Residue Number Systems: Theory and Implementations. Imperial College Press, 2007. [3] P.V.A. Mohan. Residue Number Systems: Algorithms and Architectures. Kluwer Academic, 2002. [4] T. Stouratitis and V. Paliouras, "Considering the alternatives in lowpower design," IEEE Circuits and Devices, vol. 7, pp. 23, Jul. 2001. [CrossRef] [Web of Science Times Cited 52] [SCOPUS Times Cited 73] [5] M.A. Soderstrand and et al. Residue number system arithmetic: modern applications in digital signal processing. IEEE Press, 1986. [6] R. Conway and J. Nelson, "Improved RNS FIR Filter Architectures," IEEE Trans. Circuits and Systems-II, vol. 51, pp. 26, Jan. 2004. [CrossRef] [Web of Science Times Cited 87] [SCOPUS Times Cited 110] [7] G.C. Cardarilli, A. Nannarelli and M. Re, "Residue Number System for Low-Power DSP Applications," in Proc. of Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, 2007, pp. 1412-1416. [CrossRef] [SCOPUS Times Cited 69] [8] E. Diclaudio, F. Piazza and G. Orlandi, "Fast combinatorial RNS processors for DSP applications," IEEE Trans. Computers, vol. 44, pp. 624, May 1995. [CrossRef] [Web of Science Times Cited 57] [SCOPUS Times Cited 74] [9] K. Navi, A.S. Molahosseini, M. Esmaeildoust, "How to Teach Residue Number System to Computer Scientists and Engineers," IEEE Trans. Education, vol. 54, pp. 156, Feb. 2011. [CrossRef] [Web of Science Times Cited 44] [SCOPUS Times Cited 55] [10] A.S. Molahosseini, K. Navi, O. Hashemipour, A. Jalali, "An efficient architecture for designing reverse converters based on a general three-moduli set," Elsevier J. Systems Architecture, vol. 54, pp. 929, Oct. 2008. [CrossRef] [Web of Science Times Cited 18] [SCOPUS Times Cited 24] [11] Z. Wang, G.A. Jullien and W.C. Miller, "An Improved Residue-to-Binary Converter," IEEE Trans. Circuits and Systems-I, vol. 47, pp. 1437, Sep. 2000. [CrossRef] [SCOPUS Times Cited 1] [12] Y. Wang, X. Song, M. Aboulhamid and H. Shen, "Adder based residue to binary numbers converters for (2n-1, 2n, 2n+1)," IEEE Trans. Signal Processing, vol. 50, pp. 1772, Jul. 2002. [CrossRef] [Web of Science Times Cited 118] [SCOPUS Times Cited 163] [13] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y.Wang, "A high-speed residue-to-binary converter for three-moduli {2k, 2k -1, 2k -1-1} RNS and a scheme of its VLSI implementation," IEEE Trans. Circuits and Systems-II, vol. 47, pp. 1576, Dec. 2000. [CrossRef] [Web of Science Times Cited 61] [SCOPUS Times Cited 79] [14] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y.Wang, "A Study of the Residue-to-Binary Converters for the Three-Moduli Sets," IEEE Trans. Circuits and Systems-II, vol. 50, pp. 235, Feb. 2003. [CrossRef] [Web of Science Times Cited 56] [SCOPUS Times Cited 74] [15] P. V. A. Mohan, "RNS-To-Binary Converter for a New Three-Moduli Set {2n+1-1, 2n, 2n-1}," IEEE Trans. Circuits and Systems-II, vol. 54, pp. 775, Sep. 2007. [CrossRef] [Web of Science Times Cited 73] [SCOPUS Times Cited 96] [16] S.H. Lin, M.H. Sheu, and C.H. Wang, "Efficient VLSI Design of a Residue-to-Binary Converter for the moduli set (2n, 2n+1-1, 2n-1)," IEICE Trans. Information and Systems, vol. E91-D, pp.2058, Jul. 2008. [CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 18] [17] A.S. Molahosseini, C. Dadkhah, K. Navi, M. Eshghi, "Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n-1, 2n+1-1} and {22n, 2n-1, 2n-1-1}," IEICE Trans. Information and Systems, vol. E92-D, pp. 1628, Sep. 2009. [CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 15] [18] M. Bhardwaj , T. Srikanthan, C.T. Clarke, "A reverse converter for the 4-moduli superset {2n-1, 2n, 2n+1, 2n+1+1}," in Proc. of IEEE Symposium on Computer Arithmetic, Adelaide, 1999, pp. 168-175. [CrossRef] [Web of Science Times Cited 24] [19] A.P. Vinod and A.B. Premkumar, "A residue to binary converter for the 4-moduli superset {2n-1, 2n, 2n+1, 2n+1-1}," J. Circuits, Systems and Computers, vol. 10, pp. 85, 2000. [CrossRef] [Web of Science Times Cited 46] [SCOPUS Times Cited 51] [20] P. V. A. Mohan and A. B. Premkumar, "RNS-to-Binary Converters for Two Four-Moduli Set {2n-1, 2n, 2n+1, 2n+1-1} and {2n-1, 2n, 2n+1, 2n+1+1}," IEEE Trans. Circuits and Systems-I, vol. 54, pp. 1245, Jun. 2007. [CrossRef] [Web of Science Times Cited 84] [SCOPUS Times Cited 98] [21] M.H. Sheu, S.H. Lin, C. Chen and S.W. Yang, "An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3)," IEEE Trans. Circuits and Systems-II, vol. 51, pp. 152, Mar. 2004. [CrossRef] [Web of Science Times Cited 46] [SCOPUS Times Cited 63] [22] P.V.A. Mohan, "New reverse converters for the moduli set {2n -3, 2n -1, 2n +1, 2n +3}," Elsevier J. Electronics and Communications (AEU), vol. 62, pp. 643, Oct. 2008. [CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 36] [23] B. Cao, C. H. Chang and T. Srikanthan, "An Efficient Reverse Converter for the 4-Moduli Set {2n-1, 2n, 2n+1, 22n+1} Based on the New Chinese Remainder Theorem," IEEE Trans. Circuits and Systems-I, vol. 50, pp. 1296, Oct. 2003. [CrossRef] [Web of Science Times Cited 89] [SCOPUS Times Cited 107] [24] W. Zhang , P. Siy, "An efficient design of residue to binary converter for four moduli set (2n-1,2n+1, 22n-2, 22n+1-3) based on new CRT II," Elsevier J. Information Sciences, vol. 178, pp. 264, Jan. 2008. [CrossRef] [Web of Science Times Cited 26] [SCOPUS Times Cited 30] [25] A.S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei, S. Timarchi, "Efficient Reverse Converter Designs for the New 4-Moduli Sets {2n¬-1, 2n, 2n+1, 22n+1-1} and {2n-1, 2n+1, 22n, 22n+1} Based on New CRTs," IEEE Trans. Circuits and Systems-I, vol. 57, pp. 823, Apr. 2010. [CrossRef] [Web of Science Times Cited 86] [SCOPUS Times Cited 105] [26] B. Cao, C.H. Chang and T. Srikanthan, "A Residue-to-Binary Converter for a New Five-Moduli Set," IEEE Trans. Circuits and Systems-I, vol. 54, pp. 1041, May 2007. [CrossRef] [Web of Science Times Cited 69] [SCOPUS Times Cited 92] [27] A.S. Molahosseini, C. Dadkhah and K. Navi "A New Five-Moduli Set for Efficient Hardware Implementation of the Reverse Converter," IEICE Electronics Express, vol. 6, pp. 1006, Jul. 2009. [CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 16] [28] Y. Wang, "Residue-to-Binary Converters Based on New Chinese remainder theorems," IEEE Trans. Circuits and Systems-II, vol. 47, pp. 197, Mar. 2000. [CrossRef] [Web of Science Times Cited 98] [SCOPUS Times Cited 135] [29] A. A. Hiasat, "VLSI implementation of New Arithmetic Residue to Binary decoders," IEEE Trans. VLSI Systems, vol. 13, pp. 153, Jan. 2005. [CrossRef] [Web of Science Times Cited 40] [SCOPUS Times Cited 49] [30] K. H. Rosen. Elementary Number Theory and Its Application. Addison-Wesley, 1988. [31] S.J. Piestrak, "A high speed realization of a residue to binary converter," IEEE Trans. Circuits and Systems-II, vol. 42, pp. 661, Oct. 1995. [CrossRef] [Web of Science Times Cited 114] [SCOPUS Times Cited 130] [32] S. J. Piestrak, "Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Computers, vol. 423, pp. 68, Jan. 1994. [CrossRef] [Web of Science Times Cited 139] [SCOPUS Times Cited 168] Web of Science® Citations for all references: 1,498 TCR SCOPUS® Citations for all references: 1,931 TCR Web of Science® Average Citations per reference: 45 ACR SCOPUS® Average Citations per reference: 59 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-17 13:35 in 182 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site. |
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.