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Improving Multicore Architectures by Selective Value Prediction of High-Latency Arithmetic InstructionsBUDULECI, C.   , GELLERT, A. , FLOREA, A. , BRAD, R. |
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Author keywords
multicore processing, computer simulation, prediction methods, benchmark testing, microprocessors
References keywords
prediction(22), gellert(12), architecture(10), vintan(8), comput(8), florea(7), sibiu(6), selective(6), microarchitecture(6), micro(6)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2024-05-31
Volume 24, Issue 2, Year 2024, On page(s): 61 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2024.02007
Web of Science Accession Number: 001242091800007
SCOPUS ID: 85191685636
Abstract
This work is an original contribution consisting in the implementation and evaluation of a selective value predictor in a multicore environment, with focus on long latency arithmetical instructions, having the goal to break the dataflow bottleneck of each core, thus increasing the overall performance. The Sniper simulator was used to augment the Intel Nehalem architecture with a value predictor and to estimate the computing performance, area of integration, power consumption, energy efficiency and chip temperature for the enhanced architecture. We run simulations and study the impact of the number of values which are used for prediction for each instruction. By increasing the history length, we measured on average more than 3 % increase in performance (core speed-up), a reduction in chip temperature from 57.8 C to 56.17 C, and lower energy consumption in most cases compared with the baseline configuration. We also realized a comparison between the value prediction and dynamic instruction reuse techniques in equitable condition (to exploit the same value locality), where we highlight the advantages and disadvantages of each technique in the given context. |
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| [1] C. Buduleci, A. Gellert, and A. Florea, "Selective high-latency arithmetic instruction reuse in multicore processors," in 2023 27th International Conference on System Theory, Control and Computing (ICSTCC), Timisoara, Romania: IEEE, Oct. 2023, pp. 410-415. [CrossRef] [SCOPUS Times Cited 2] [2] T. E. Carlson, W. Heirman, S. Eyerman, I. Hur, and L. Eeckhout, "An evaluation of high-level mechanistic core models," ACM Trans. Archit. Code Optim., vol. 11, no. 3, pp. 1-25, Oct. 2014. [CrossRef] [Web of Science Times Cited 194] [SCOPUS Times Cited 242] [3] J. E. Miller, H. Kasture, G. Kurian, C. Gruenwald, N. Beckmann, C. Celio, J. Eastep, and A. Agarwal, "Graphite: A distributed parallel simulator for multicores," in HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, Bangalore: IEEE, Jan. 2010, pp. 1-12. [CrossRef] [SCOPUS Times Cited 362] [4] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, "The gem5 simulator," SIGARCH Comput. Archit. News, vol. 39, no. 2, pp. 1-7, May 2011. [CrossRef] [5] M. Lipp, M. Schwarz, D. Gruss, T. Prescher, W. Haas, S. Mangard, P. Kocher, D. Genkin, Y. Yarom, and M. Hamburg, "Meltdown." arXiv, Jan. 03, 2018. Accessed: Feb. 26, 2024. [CrossRef] [6] P. Kocher, D. Genkin, D. Gruss, W. Haas, M. Hamburg, M. Lipp, S. Mangard, T. Prescher, M. Schwarz, and Y. Yarom, "Spectre attacks: Exploiting speculative execution," 2018. [CrossRef] [7] R. Sheikh, R. Cammarota, and W. Ruan, "Value prediction for security (VPsec): Countering fault attacks in modern microprocessors," in 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC: IEEE, Apr. 2018, pp. 235-238. [CrossRef] [SCOPUS Times Cited 4] [8] S. Deng and J. Szefer, "New predictor-based attacks in processors," in 2021 58th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA: IEEE, Dec. 2021, pp. 697-702. [CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 4] [9] M. M. K. Martin, D. J. Sorin, H. W. Cain, M. D. Hill, and M. H. Lipasti, "Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing," in Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34, Austin, TX, USA: IEEE Comput. Soc, 2001, pp. 328-337. [CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 43] [10] L. Widgen and E. Sowadsky, "Operand cache addressed by the instruction address for reducing latency of read instruction," U.S. Patent US5919256A, Jul. 06, 1999 [11] F. Gabbay and A. Mendelson, "System and method for concurrent processing," U.S. Patent US5996060A, Nov. 30, 1999 [12] M. H. Lipasti and J. P. Shen, "Exceeding the dataflow limit via value prediction," in Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29, Paris, France: IEEE Comput. Soc. Press, 1996, pp. 226-237. [CrossRef] [Web of Science Times Cited 143] [13] M. H. Lipasti, C. B. Wilkerson, and J. P. Shen, "Value locality and load value prediction," SIGPLAN Not., vol. 31, no. 9, pp. 138-147, Sep. 1996. [CrossRef] [Web of Science Times Cited 102] [SCOPUS Times Cited 150] [14] Y. Sazeides and J. E. Smith, "The predictability of data values," in Proceedings of 30th Annual International Symposium on Microarchitecture, Research Triangle Park, NC, USA: IEEE Comput. Soc, 1997, pp. 248-258. [CrossRef] [Web of Science Times Cited 139] [15] F. Gabbay and A. Mendelson, "Speculative execution based on value prediction," Technion - Israel Institute of Technology, EE Department TR 1080, 1996 [16] L. N. Vintan, A. Florea, and A. Gellert, "Focalising dynamic value prediction to CPU's context," IEE Proc., Comput. Digit. Tech., vol. 152, no. 4, p. 473, 2005. [CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 7] [17] L. Yang, L. Huang, R. Yan, N. Xiao, S. Ma, L. Shen, and W. Xu, "Stride equality prediction for value speculation," IEEE Comput. Arch. Lett., vol. 21, no. 2, pp. 57-60, Jul. 2022. [CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 3] [18] A. Seznec, "Exploring value prediction with the eves predictor," in 1st Championship Value Prediction, Los Angeles, CA, USA, Jun. 2018 [19] B. Goeman, H. Vandierendonck, and K. De Bosschere, "Differential FCM: increasing value prediction accuracy by improving table usage efficiency," in Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, Monterrey, Mexico: IEEE Comput. Soc, 2001, pp. 207-216. [CrossRef] [Web of Science Times Cited 50] [20] N. Deshmukh, S. Verma, P. Agrawal, B. Panda, and M. Chaudhuri, "DFCM++: Augmenting DFCM with early update and data dependence-driven value estimation," in 1st Championship Value Prediction, Los Angeles, CA, USA, Jun. 2018 [21] A. Perais and A. Seznec, "Practical data value speculation for future high-end processors," in 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), Orlando, FL, USA: IEEE, Feb. 2014, pp. 428-439. [CrossRef] [SCOPUS Times Cited 54] [22] Y. Ishii, "Context-base computational value prediction with value compression," in 1st Championship Value Prediction, Los Angeles, CA, USA, Jun. 2018 [23] K. Koizumi, K. Hiraki, and M. Inaba, "H3VP: History based highly reliable hybrid value predictor," in 1st Championship Value Prediction, Los Angeles, CA, USA, Jun. 2018 [24] R. Sheikh, H. W. Cain, and R. Damodaran, "Load value prediction via path-based address prediction: avoiding mispredictions due to conflicting stores," in Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, Cambridge Massachusetts: ACM, Oct. 2017, pp. 423-435. [CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 24] [25] A. Gellert, "Advanced prediction methods integrated into speculative computer architecture," PhD Thesis, "Lucian Blaga" University of Sibiu, Computer Science Department, Sibiu, 2008 [26] A. Gellert, Beyond the limits of modern processors. Bucharest Matrix Rom, 2008 [27] A. Gellert, A. Florea, and L. Vintan, "Exploiting selective instruction reuse and value prediction in a superscalar architecture," Journal of Systems Architecture, vol. 55, no. 3, pp. 188-195, Mar. 2009. [CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 10] [28] A. Gellert, G. Palermo, V. Zaccaria, A. Florea, L. Vintan, and C. Silvano, "Energy-performance design space exploration in SMT architectures exploiting selective load value predictions," in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden: IEEE, Mar. 2010, pp. 271-274. [CrossRef] [SCOPUS Times Cited 15] [29] A. Gellert, H. Calborean, L. Vintan, and A. Florea, "Multi-objective optimisations for a superscalar architecture with selective value prediction," IET Comput. Digit. Tech., vol. 6, no. 4, p. 205, 2012. [CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 11] [30] Gellert, A. Florea, U. Fiore, P. Zanetti, and L. Vintan, "Performance and energy optimisation in CPUs through fuzzy knowledge representation," Information Sciences, vol. 476, pp. 375-391, Feb. 2019. [CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 18] [31] A. Gellert, "Prediction-based modeling and estimation in advanced computing systems," Habilitation Thesis, "Lucian Blaga" University of Sibiu, Sibiu, 2023 [32] A. Gellert and L. Vintan, "A multicore architecture with selective load value prediction," Proceedings of The Romanian Academy, Series A: Mathematics, Physics, Technical Sciences, Information Science, vol. 19, no. 4, pp. 597-604, 2018 [33] A. Gellert, M. Vintan, and L. Vintan, "Perceptron-based selective load value prediction in a multicore architecture," Romanian Journal of Information Science and Technology, vol. 22, no. 3-4, pp. 215-227, 2019 [34] C. Buduleci, A. Gellert, A. Florea, and A. Matei, "Extending sniper with support to access operand values: A case study on reusability measurement," in 2022 23rd International Carpathian Control Conference (ICCC), Sinaia, Romania: IEEE, May 2022, pp. 70-75. [CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 2] [35] A. Fog, "The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers," Technical University of Denmark, Nov. 2022 [36] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen and N. P. Jouppi, "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, NY, USA, 2009, pp. 469-480 [CrossRef] [SCOPUS Times Cited 2012] [37] S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in Proceedings 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy: ACM, 1995, pp. 24-36. [CrossRef] [38] H. Calborean, "Multi-objective optimization of advanced computer architectures using domain-knowledge," PhD Thesis, "Lucian Blaga" University of Sibiu, Sibiu, 2011 [39] E. J. Gomez-Hernandez, J. M. Cebrian, S. Kaxiras, and A. Ros, "Splash-4: A modern benchmark suite with lock-free constructs," in 2022 IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, USA: IEEE, Nov. 2022, pp. 51-64. [CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 4] Web of Science® Citations for all references: 704 TCR SCOPUS® Citations for all references: 2,967 TCR Web of Science® Average Citations per reference: 17 ACR SCOPUS® Average Citations per reference: 72 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-20 13:13 in 169 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. 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Stefan cel Mare University of Suceava, Romania
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
