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Efficient and Power-Aware Design of a Novel Sparse Kogge-Stone Adder using Hybrid Carry Prefix Generator AdderKHAN, A.   , WAIRYA, S. |
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Author keywords
circuit simulation, circuit topology, digital circuits, parallel architectures, very large scale integration
References keywords
adder(20), systems(12), carry(12), high(11), design(11), adders(11), speed(9), circuits(8), prefix(7), parallel(7)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2024-02-29
Volume 24, Issue 1, Year 2024, On page(s): 71 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2024.01008
Web of Science Accession Number: 001178765900007
SCOPUS ID: 85189442408
Abstract
This paper presents a novel Sparse Kogge-Stone adder architecture with a sparsity factor of 2, offering a compelling solution to the challenges faced by parallel prefix adders. The superior performance is achieved by including the hybrid carry prefix generator adder (HCPGA), which leads to the elimination of redundant components, and improvements in power consumption and circuit area without compromising computation speed. The proposed hybrid architecture efficiently generates carry prefixes that negates the need for the conventional generate and propagate block, resulting in reduced computational complexity. The effectiveness of the proposed architecture has been extensively validated using Cadence Virtuoso in the 45nm technology node. In addition to evaluating standard performance parameters such as power, delay, and area, comprehensive Monte Carlo simulations and process corner analyses have been performed to ensure the robustness and reliability of the design. Furthermore, the practical application of the proposed architecture has been demonstrated by integrating it into a digital multiplier architecture, showcasing its potential to enhance the computational capabilities of complex arithmetic circuits. This research contributes to the advancement of efficient adder designs for high-performance computing applications, making it highly beneficial and relevant for modern digital circuit designs. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
