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Quadrature Signal Generator with Improved DC Offset CompensationSTOJIC, D. |
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Author keywords
estimation, frequency locked loops, nonlinear control systems, phase locked loops, power conversion
References keywords
electronics(19), phase(18), power(16), offset(16), single(8), rejection(6), locked(6), access(6), systems(5), grid(5)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2021-08-31
Volume 21, Issue 3, Year 2021, On page(s): 65 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2021.03008
Web of Science Accession Number: 000691632000008
SCOPUS ID: 85114777511
Abstract
In this paper a second order generalized integrator (SOGI) based quadrature signal generator (QSG) is proposed with the improved DC offset compensation parameter tuning procedure. Namely, for the conventional DC rejection technique, which comprises an integrator (I) included in the SOGI, the modified parameter tuning procedure is proposed based on the set QSG response damping factor value. In this way, when compared to existing QSG tuning techniques based on empirical trial-and-error approach, simplified parameter tuning procedure is proposed based on proposed parametric equations, which enable improved QSG performance verified by simulation and experimental runs by a single-phase phase-locked loop PLL. In this way the increased SOGI based QSG DC offset compensation speed can be achieved, which is critical in various types of single phase PLL applications. |
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[1] M. Xie, H. Wen, C. Zhu, and Y. Yang, "DC offset rejection improvement in single-phase SOGI-PLL algorithms: Methods review and experimental evaluation," IEEE Access, vol. 5, pp. 12810-12819, 2017. [CrossRef] [Web of Science Times Cited 113] [SCOPUS Times Cited 132] [2] M. Karimi-Ghartemani, S. A. Khajehoddin, P. K. Jain, A. Bakhshai, and M. Mojiri, "Addressing DC component in PLL and notch filter algorithms," IEEE Transactions on Power Electronics, vol. 27, pp. 78-86, 2012. [CrossRef] [Web of Science Times Cited 281] [SCOPUS Times Cited 353] [3] S. Golestan, J. M. Guerrero, and G. B. Gharehpetian, "Five approaches to deal with problem of DC offset in phase-locked loop algorithms: Design considerations and performance evaluations," IEEE Transactions on Power Electronics, vol. 31, pp. 648-661, 2016. [CrossRef] [Web of Science Times Cited 109] [SCOPUS Times Cited 132] [4] S. Golestan, J. M. Guerrero, and J. C. Vasquez, "Three-phase PLLs: A review of recent advances," IEEE Transactions on Power Electronics, vol. 32, pp. 1894-1907, 2017. [CrossRef] [Web of Science Times Cited 512] [SCOPUS Times Cited 643] [5] S. Golestan, J. M. Guerrero, and J. C. Vasquez, "Single-phase PLLs: A review of recent advances," IEEE Transactions on Power Electronics, vol. 32, pp. 9013-9030, 2017. [CrossRef] [Web of Science Times Cited 269] [SCOPUS Times Cited 347] [6] Y. Han, M. Luo, X. Zhao, J. M. Guerrero, and L. Xu, "Comparative performance evaluation of orthogonal-signal-generators-based single-phase PLL algorithms-A survey," IEEE Transactions on Power Electronics, vol. 31, pp. 3932-3944, 2016. [CrossRef] [Web of Science Times Cited 274] [SCOPUS Times Cited 330] [7] X. Huang, L. Dong, F. Xiao, and X. Liao, "A new orthogonal signal generator with DC offset rejection for single-phase phase locked loops," Journal of Power Electronics, vol. 16, pp. 310-318, 2016. [CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 5] [8] C. Zhang, X. Zhao, X. Wang, X. Chai, Z. Zhang, and X. Guo, "A grid synchronisation PLL method based on mixed second-and third-order generalised integrator for DC-offset elimination and frequency adaptability," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 6, no. 3, pp. 1517-1526, 2018. [CrossRef] [Web of Science Times Cited 137] [SCOPUS Times Cited 181] [9] Z. Xin, X. Wang, Z. Qin, M. Lu, P. C. Loh, and F. Blaabjerg, "An improved second-order generalised integrator based quadrature signal generator," IEEE Transactions on Power Electronics, vol. 31, pp. 8068-8073, 2016. [CrossRef] [Web of Science Times Cited 192] [SCOPUS Times Cited 234] [10] S. Golestan, S. Y. Mousazadeh, J. M. Guerrero, and J. C. Vasquez, "A critical examination of frequency-fixed second-order generalised integrator-based phase-locked loops," IEEE Transactions on Power Electronics, vol. 32, pp. 6666-6672, 2017. [CrossRef] [Web of Science Times Cited 65] [SCOPUS Times Cited 76] [11] P. Kanjiya, V. M. Khadkikar, and M. S. ElMoursi, "Adaptive low-pass filter based DC offset removal technique for three-phase PLLs," IEEE Transactions on Industrial Electronics, vol. 65, no. 11, pp. 9025 - 9029, 2018. [CrossRef] [Web of Science Times Cited 31] [SCOPUS Times Cited 42] [12] T. Ngo, Q. Nguyen, and S. Santoso, "Improving performance of single-phase SOGI-FLL under DC-offset voltage condition," in Industrial Electronics Society, IECON 2014-40th Annual Conference of the IEEE, 2014, pp. 1537-1541. [CrossRef] [SCOPUS Times Cited 32] [13] M. Ciobotaru, R. Teodorescu, and V. G. Agelidis, "Offset rejection for PLL based synchronisation in grid-connected converters," in Applied Power Electronics Conference and Exposition, 2008. APEC 2008. Twenty-Third Annual IEEE, 2008, pp. 1611-1617. [CrossRef] [Web of Science Times Cited 97] [SCOPUS Times Cited 152] [14] A. Kulkarni and V. John, "Design of a fast response time single-phase PLL with dc offset rejection capability," Electric Power Systems Research, vol. 145, pp. 35-43, 2017. [CrossRef] [Web of Science Times Cited 37] [SCOPUS Times Cited 41] [15] K. J. Astrom and R. M. Murray, Feedback systems: An introduction for scientists and engineers. Princeton University press, 2010. [CrossRef] [16] S. Golestan, M. Monfared, F. D. Freijedo, and J. M. Guerrero, "Dynamics assessment of advanced single-phase PLL structures," IEEE Transactions on Industrial Electronics, vol. 60, pp. 2167-2177, 2013. [CrossRef] [Web of Science Times Cited 280] [SCOPUS Times Cited 332] [17] Golestan, S., Guerrero, J.M., and Gharehpetian, G.B., "Five approaches to deal with problem of DC offset in phase-locked loop algorithms: Design considerations and performance evaluations", IEEE Transactions on Power Electronics, vol. 31, pp. 648-661, 2016. [CrossRef] [Web of Science Times Cited 109] [SCOPUS Times Cited 132] [18] Golestan, Saeed, Josep M. Guerrero, and Juan C. Vasquez, "DC-offset rejection in phase-locked loops: A novel approach," IEEE Transactions on Industrial Electronics, vol. 63, no. 8, pp. 4942-4946, 2016. [CrossRef] [Web of Science Times Cited 109] [SCOPUS Times Cited 132] [19] Hui, Nanmu, Dazhi Wang, and Yunlu Li, "A novel hybrid filter-based PLL to eliminate effect of input harmonics and DC offset," IEEE Access, vol. 6, pp. 19762-19773, 2018. [CrossRef] [Web of Science Times Cited 35] [SCOPUS Times Cited 44] [20] Ali, Zunaib, Nicholas Christofides, Lenos Hadjidemetriou, and Elias Kyriakides, "Design of an advanced PLL for accurate phase angle extraction under grid voltage HIHs and DC offset," IET Power Electronics, vol. 11, no. 6, pp. 995-1008, 2017. [CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 37] [21] Trinh, Quoc Nam, Peng Wang, Yi Tang, Leong Hai Koh, and Fook Hoong Choo, "Compensation of DC offset and scaling errors in voltage and current measurements of three-phase AC/DC converters," IEEE Transactions on Power Electronics, vol. 33, no. 6, pp. 5401-5414, 2017. [CrossRef] [Web of Science Times Cited 45] [SCOPUS Times Cited 49] [22] Li, Yunlu, Dazhi Wang, Yi Ning, and Nanmu Hui, "DC-offset elimination method for grid synchronization," Electronics Letters, vol. 53, no. 5, pp. 335-337, 2017. [CrossRef] [Web of Science Times Cited 137] [SCOPUS Times Cited 181] [23] Bai, Yu, Xiaoqiang Guo, Baocheng Wang, and Yongjian Li, "Fully digital grid synchronization under harmonics and unbalanced conditions," IEEE Access, no. 7, pp. 109969-109981, 2019. [CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 12] [24] Trinh, Quoc Nam, Peng Wang, and Fook Hoong Choo, "An improved control strategy of three-phase PWM rectifiers under input voltage distortions and DC-offset measurement errors," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 5, no. 3, pp. 1164-1176, 2017. [CrossRef] [Web of Science Times Cited 28] [SCOPUS Times Cited 39] [25] Kherbachi, Abdelhammid, Aissa Chouder, Ahmed Bendib, Kamel Kara, and Said Barkat, "Enhanced structure of second-order generalized integrator frequency-locked loop suitable for DC-offset rejection in single-phase systems," Electric Power Systems Research, vol. 170, pp. 348-357, 2019. [CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 53] [26] S. Preitl and R.-E. Precup, "An extension of tuning relations after Symmetrical Optimum method for PI and PID controllers," Automatica, vol. 35, no. 10, pp. 1731-1736, Oct. 1999. [CrossRef] [Web of Science Times Cited 155] [SCOPUS Times Cited 220] [27] Haidegger, Tamas, Levente Kovacs, Radu-Emil Precup, Stefan Preitl, Balazs Benyo, and Zoltan Benyo, "Cascade control for telerobotic systems serving space medicine," IFAC Proceedings, vol. 44, no. 1, 2011, pp. 3759-3764. [CrossRef] [SCOPUS Times Cited 106] Web of Science® Citations for all references: 3,103 TCR SCOPUS® Citations for all references: 4,037 TCR Web of Science® Average Citations per reference: 111 ACR SCOPUS® Average Citations per reference: 144 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-16 12:11 in 182 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. 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