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JCR Impact Factor: 0.700
JCR 5-Year IF: 0.700
SCOPUS CiteScore: 1.8
Issues per year: 4
Current issue: May 2024
Next issue: Aug 2024
Avg review time: 59 days
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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2024-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2023. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.700 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.600.

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

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  2/2010 - 9

Conceptual Implementation of Sample Rate Convertors for DACs

ANTONESEI, G. See more information about ANTONESEI, G. on SCOPUS See more information about ANTONESEI, G. on IEEExplore See more information about ANTONESEI, G. on Web of Science, TURCU, C. See more information about  TURCU, C. on SCOPUS See more information about  TURCU, C. on SCOPUS See more information about TURCU, C. on Web of Science, GRAUR, A. See more information about GRAUR, A. on SCOPUS See more information about GRAUR, A. on SCOPUS See more information about GRAUR, A. on Web of Science
 
View the paper record and citations in View the paper record and citations in Google Scholar
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (2,568 KB) | Citation | Downloads: 1,384 | Views: 5,118

Author keywords
DAC, CIC, mobile phone audio subsystem, multirate filtering, sample rate converter

References keywords
No relevant keywords could be extracted from the references.

About this article
Date of Publication: 2010-05-31
Volume 10, Issue 2, Year 2010, On page(s): 53 - 60
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2010.02009
Web of Science Accession Number: 000280312600009
SCOPUS ID: 77954631109

Abstract
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Full text preview
One of most common and difficult challenge when creating a single SoC with digital (sub)sections is caused by the various master clock (MCLK) frequencies that each individual IC had originally. There are several methods to solve this, but when constraint by price and power consumption, the design engineers must find the optimum one. The sample rate converters (SRC) are an example of solution that can simplify the architecture in some of these cases. However, even for the SRCs themselves, we need to come up with novel and efficient architectures. This paper presents such an example from mobile phones chips on how to successfully mix on the same silicon, an audio sigma-delta DAC which should support all the standard audio rates using a 13MHz MCLK frequency imposed by the RF section incorporated inside the same chip. The document will go from showing the top-level digital signal processing down to the actual hardware implementation.


References | Cited By  «-- Click to see who has cited this paper

[1] L. Bening, H. Foster, "Principles of verifiable RTL design : a functional coding style supporting verification processes in Verilog", 2nd edition, Kluwer Academic Publishers Norwell, MA, USA, 2001. [PermaLink]

[2] G. Antonesei, C. Turcu, A. Graur, "Basic Consideration for Signal Processing Solutions Used in Sigma-delta Based ADC and DAC Converters", Advances in Electrical and Computer Engineering, vol. 10, number 1,
[CrossRef] [Full Text] [Web of Science Times Cited 2] [SCOPUS Times Cited 3]


[3] P. Schniter, Noble Identities, Available: Temporary on-line reference link removed - see the PDF document

[4] G. Antonesei, "Sample Rate Converter For Reducing The Sampling Frequency Of A Signal By A Fractional Number", US Patent 7236110, 2007.

References Weight

Web of Science® Citations for all references: 2 TCR
SCOPUS® Citations for all references: 3 TCR

Web of Science® Average Citations per reference: 1 ACR
SCOPUS® Average Citations per reference: 1 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-07-13 18:13 in 10 seconds.




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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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