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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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A Novel Analytical Model for Network-on-Chip using Semi-Markov Process

WANG, J. See more information about WANG, J. on SCOPUS See more information about WANG, J. on IEEExplore See more information about WANG, J. on Web of Science, LI, Y. See more information about  LI, Y. on SCOPUS See more information about  LI, Y. on SCOPUS See more information about LI, Y. on Web of Science, PENG, Q. See more information about PENG, Q. on SCOPUS See more information about PENG, Q. on SCOPUS See more information about PENG, Q. on Web of Science
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Author keywords
multiprocessor interconnection, network-on-chip, semi-markov process, modeling, computer aided analysis

References keywords
chip(13), design(11), systems(9), networks(8), network(8), architecture(6), analytical(5), analysis(5), test(4), automation(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2011-02-27
Volume 11, Issue 1, Year 2011, On page(s): 111 - 118
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2011.01018
Web of Science Accession Number: 000288761800018
SCOPUS ID: 79955967326

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Network-on-Chip (NoC) communication architecture is proposed to resolve the bottleneck of Multi-processor communication in a single chip. In this paper, a performance analytical model using Semi-Markov Process (SMP) is presented to obtain the NoC performance. More precisely, given the related parameters, SMP is used to describe the behavior of each channel and the header flit routing time on each channel can be calculated by analyzing the SMP. Then, the average packet latency in NoC can be calculated. The accuracy of our model is illustrated through simulation. Indeed, the experimental results show that the proposed model can be used to obtain NoC performance and it performs better than the state-of-art models. Therefore, our model can be used as a useful tool to guide the NoC design process.

References | Cited By  «-- Click to see who has cited this paper

[1] S. Kumar, A. Jantsch, and J-P. Soininen, et al: "A Network on Chip Architecture and Design Methodology". IEEE Computer Society Annual Symposium on VLSI, 2002. Pittsburgh, PA, USA, pp. 105-112, 2002.

[2] Jian Liu, LiRong Zheng, Hannu Tenhunen: "Interconnect intellectual property for Network-on-Chip". Journal of Systems Architecture, Vol. 50, pp. 65-79. 2004.
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 40]

[3] A. Sheibanyrad, I. M. Panades, and A. Greiner,: "Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture". Design, Automation & Test in Europe conference & Exhibition, 2007, Nice, France, pp. 1-6, 2007.

[4] Jingcao Hu, Ogras, U.Y., Marculescu, R.; "Application-specific buffer space allocation for networks-on-chip router design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, Issue 12, pp. 2919-2933. 2006.
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[6] Murali, S., and De Micheli, G.: "Bandwidth-constrained mapping of cores onto NoC architectures". Design Automation and Test in Europe conference & Exhibition, Paris, France. pp. 896-901, 2004.

[7] Eisley, N., and Peh, L.-S.: "High-level power analysis for on-chip networks". Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, Washington DC, pp. 104-115. 2004.

[8] Jantsch, A., Lauter, R. and Vitkowski, A.: "Power analysis of link level and end-to-end data protection in networks on chip". IEEE International Symposium on Circuits and Systems, 2005. New York, USA, pp. 1770-1773. 2005.
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 28]

[9] Moadeli, M., Shahrabi, A., Vanderbauwhede, W. and Ould-Khaoua, M.: "An analytical performance model for the spidergon noc". 21st International Conference on Advanced Information Networking and Applications, 2007. Niagara Falls, Canada, pp. 1014-1021, 2007

[10] Ogras, U. Y. and Marculescu, R.: "Analytical router modeling for networks-on-chip performance analysis". DATE 2007, Nice, France. pp. 1-6. 2007.

[11] Guz, Z., Walter, I., Bolotin, E., Cidon, I., Ginosar, R. and Kolodny, A.: "Efficient link capacity and qos design for network-on-chip". Design, Automation and Test in Europe, 2006. Munich, Germany. pp. 1-6, 2006.

[12] Khonsari, A., Mohammad, R., Aghajani, A. T., et al: "Mathematical analysis of buffer sizing for network-on-chips under multimedia traffic". IEEE International Conference on Computer Design, 2008, California, USA, pp. 150-155, 2008.
[CrossRef] [SCOPUS Times Cited 11]

[13] Ting-Chun Huang, Ogras, U. Y., Marculescu, R.: "Virtual channels planning for networks-on-chip". International Symposium on Quality Electronic Design, 2007, San Jose, USA. pp. 879-884, 2007.

[14] Bahn, J. H., Bagherzadeh, N.: "Design of simulation and analytical models for a 2d-meshed asymmetric adaptive router". Computers & Digital Techniques, IET. vol. 2, no 1, pp. 63-73, 2008.
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 11]

[15] Foroutan, S., Thonnart, Y., Hersemeule, R. and Jerraya, A.: "An Analytical Method for Evaluating Network-on-Chip Performance". Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. Dresden, Germany, pp. 1629-1632, 2010.

[16] Leonard Kleinrock: "Queueing Systems, Volume I: Theory". Wiley Interscience, New York, 1975.

[17] Dally, W. J., and Seitz, C. L.: "Deadlock-free message routing in multiprocessor interconnection networks". IEEE Transactions on Computers, vol C-36. pp. 547-553, 1987.
[CrossRef] [SCOPUS Times Cited 1389]

[18] Jean-Yves Le Boudec and Patrick Thiran: "Network calculus: A theory of deterministic queuing systems for the internet". Springer. 2001.

[19] Bakhouya, M., Suboh, S., Gaber, J. and El-Ghazawi, T.: "Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus". The 3rd ACM/IEEE International Symposium on Networks-on-Chip, San Diego, USA. pp. 74-79, 2009.

[20] Lahiri, K., Raghunathan, A. and Lakshminarayana, G.: "The lotterybus on-chip communication architecture". IEEE Transactions on Very Large Scale Integration Systems. Vol 14, pp. 596-608, 2006.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 48]

[21] Chung, C.M., Chiang, D. A., and Qing, Y.: "Comparative analysis of different arbitration protocols for multiple-bus multiprocessors". Journal of Computer Science and Technology. vol 3, pp. 313-325, 1996.
[CrossRef] [SCOPUS Times Cited 8]

[22] Ni, M. L., and McKinley, K. P.: "A survey of wormhole routing techniques in direct networks". Computer. vol. 26, no. 2, pp. 62-76, 1993.
[CrossRef] [Web of Science Times Cited 469] [SCOPUS Times Cited 998]

[23] Mudge, T. N., Al-Sadoun, H. B., and Makrucki, B. A.: "Memory-interference model for multiprocessors based on semi-Markov processes". IEE Proceedings E Computers and Digital Techniques, vol 134, pp. 203-214, 1987.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 3]

References Weight

Web of Science® Citations for all references: 649 TCR
SCOPUS® Citations for all references: 2,707 TCR

Web of Science® Average Citations per reference: 28 ACR
SCOPUS® Average Citations per reference: 118 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2022-01-24 19:09 in 71 seconds.

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