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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
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ROMANIA

Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  4/2012 - 14
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Design of Processor Array Based on an Optimized Multiprojection Approach

CAMPOS, J.-M See more information about CAMPOS, J.-M on SCOPUS See more information about CAMPOS, J.-M on IEEExplore See more information about CAMPOS, J.-M on Web of Science, CUMPLIDO, R. See more information about CUMPLIDO, R. on SCOPUS See more information about CUMPLIDO, R. on SCOPUS See more information about CUMPLIDO, R. on Web of Science
 
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Download PDF pdficon (898 KB) | Citation | Downloads: 805 | Views: 4,448

Author keywords
data flow computing, parallel architectures, parallel machines, parallel processing, systolic arrays

References keywords
parallel(14), loop(6), programming(5), model(5), feautrier(5), automatic(5), vasilache(4), scheduling(4), loops(4), computing(4)
No common words between the references section and the paper title.

About this article
Date of Publication: 2012-11-30
Volume 12, Issue 4, Year 2012, On page(s): 87 - 92
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2012.04014
Web of Science Accession Number: 000312128400014
SCOPUS ID: 84872811165

Abstract
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Parallelization methodologies allow to automate the process of designing optimal processor arrays based on mathematical representations of the algorithm to be implemented. In this work, an optimized multiprojection approach based on the Polytope model is proposed as well as an automated way for getting the scheduler and the allocator vectors. Using a recurrence equations representation, three key criteria for choosing the characteristics of the final implementation are also proposed. As a case of study, the methodology is applied on a matrix-vector multiplication example. Results and relevance of the proposed methodology are finally discussed.


References | Cited By  «-- Click to see who has cited this paper

[1] S. Y. Kung. "VLSI Array Processors". Printice Hall, Englewood Cliffs, New Jersey, 1988.

[2] Christian Lengauer. "Loop Parallelization in the Polytope Model". In Eike Best, editor, Proceedings of the 4th International Conference on Concurrency Theory (CONCUR), volume 715 of Lecture Notes in Computer Science (LNCS), pages 398-416, Hildesheim, Germany, August 1993. [CiteSeerX]

[3] Alain Darte. "Mathematical tools for loop transformations: From systems of uniform recurrence equations to the polytope model". In M. H. Heath, A. Ranade, and R. S. Schreiber, editors, Algorithms for Parallel Processing, volume 105 of IMA. Volumes in Mathematics and its Applications, pages 147-183. Springer Verlag, 1998. [CiteSeerX]

[4] S.P.K. Nookala and Tanguy Risset. "A library for Z-polyhedral operations". Technical Report PI 1330, IRISA, Rennes, France, 2000.

[5] Gautam Gupta and Sanjay Rajopadhye. "The z-polyhedral model". In ACM SIGPLAN symposium on Principles and Practice of Parallel Programming, pages 237-248, 2007.
[CrossRef] [SCOPUS Times Cited 4]


[6] P. Feautrier. "Some efficient solutions to the affine scheduling problem: Part I, one-dimensional time". International Journal of Parallel Programming, 21(5):313-348, 1992.
[CrossRef] [Web of Science Times Cited 230] [SCOPUS Times Cited 327]


[7] P. Feautrier. "Some efficient solutions to the affine scheduling problem: Part II, multidimensional time". International Journal of Parallel Programming, 21(6):389-420, 1992.
[CrossRef] [Web of Science Times Cited 213] [SCOPUS Times Cited 282]


[8] P. Feautrier. "Toward automatic distribution". Parallel Processing Letters, 4:233-244, 1994.
[CrossRef] [SCOPUS Times Cited 47]


[9] Michele Dion and Yves Robert. "Mapping affine loop nests". Parallel Computing, 22(10):1373-1397, 1996.
[CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 16]


[10] Martin Griebl. "Automatic Parallelization of Loop Programs for Distributed Memory Architectures". University of Passau, 2004. Habilitation thesis.

[11] Martin Griebl, Paul Feautrier, and Armin Gro├člinger. "Forward communication only placements and their use for parallel program construction". In Languages and Compilers for Parallel Computing, pages 16-30. Springer- Verlag, 2005.
[CrossRef] [Web of Science Times Cited 5] [SCOPUS Times Cited 11]


[12] Frank Hannig. "Scheduling Techniques for High Throughput Loop Accelerators". Dissertation, University of Erlangen Nuremberg, Germany, August 2009. Verlag Dr. Hut, Munich, Germany.

[13] Fabien Quillere, Sanjay Vishnu Rajopadhye, and Doran Wilde. "Generation of Efficient Nested Loops from Polyhedra". International Journal of Parallel Programming, 28(5):469-498, 2000.
[CrossRef] [Web of Science Times Cited 90] [SCOPUS Times Cited 126]


[14] Paul Feautrier. "Automatic Parallelization in the Polytope Model". Technical Report 8, Laboratoire PRiSM, Universite des Versailles St- Quentin en Yvelines, 45, avenue des Etats-Unis, 78035 Versailles Cedex, France, June 1996.

[15] Albert Cohen, Sylvain Girbal, David Parello, M. Sigler, Olivier Temam, and Nicolas Vasilache. "Facilitating the search for compositions of program transformations". In ACM International conference on Supercomputing, pages 151-160, June 2005.
[CrossRef] [SCOPUS Times Cited 69]


[16] Nicolas Vasilache, Cedric Bastoul, Sylvain Girbal, and Albert Cohen. "Violated dependence analysis". In ACM International conference on Supercomputing, June 2006.
[CrossRef] [SCOPUS Times Cited 22]


[17] L.-N. Pouchet, C. Bastoul, A. Cohen, and N. Vasilache. "Iterative optimization in the polyhedral model: Part I, one-dimensional time". In International symposium on Code Generation and Optimization, March 2007.
[CrossRef] [SCOPUS Times Cited 83]


[18] Alain Darte, Leonid Khachiyan, and Yves Robert. "Linear Scheduling is Close to Optimality". In Proceedings of the International Conference on Application Specific Array Processors (ASAP), pages 37-46, Berkeley, CA, USA, August 1992.
[CrossRef]


[19] Leslie Lamport. "The parallel execution of do loops". Communications of the ACM, 17(2):83-93, 1974.
[CrossRef] [SCOPUS Times Cited 403]


[20] Kittitornkun Surin, Yu Hen Hu. "Processor Array Synthesis from Shift-Variant Deep Nested Do Loops". The Journal of Supercomputing, 24(3):229-249, 2003.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 3]


[21] Robert H. Kuhn. "Transforming Algorithms for Single-Stage and VLSI Architectures". In Workshop on Interconnection Networks for Parallel and Distributed Processing, pages 11-19, West Layfaette, IN, USA, April 1980.

[22] Michael Wolfe. "High Performance Compilers for Parallel Computing". Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1995.

[23] Nicolas Vasilache, Albert Cohen, and Louis-Noel Pouchet. 2007. "Automatic Correction of Loop Transformations". In Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques (PACT '07). IEEE Computer Society, Washington, DC, USA.
[CrossRef] [SCOPUS Times Cited 17]


[24] Uday Bondhugula, J. Ramanujam, and P. Sadayappan. 2007. "Automatic mapping of nested loops to FPGAS". In Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming (PPoPP '07). ACM, New York, NY, USA, 101-111.
[CrossRef] [SCOPUS Times Cited 25]


[25] Richard M. Karp, Raymond E. Miller, and Shmuel Winograd. "The Organization of Computations for Uniform Recurrence Equations". Journal of the Association for Computing Machinery, 14(3):563-590, 1967.
[CrossRef] [SCOPUS Times Cited 356]




References Weight

Web of Science® Citations for all references: 556 TCR
SCOPUS® Citations for all references: 1,791 TCR

Web of Science® Average Citations per reference: 21 ACR
SCOPUS® Average Citations per reference: 69 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-05-17 03:20 in 109 seconds.




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