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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  4/2012 - 3

A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture

WANG, J. See more information about WANG, J. on SCOPUS See more information about WANG, J. on IEEExplore See more information about WANG, J. on Web of Science, LI, Y. See more information about  LI, Y. on SCOPUS See more information about  LI, Y. on SCOPUS See more information about LI, Y. on Web of Science, LI, H. See more information about LI, H. on SCOPUS See more information about LI, H. on SCOPUS See more information about LI, H. on Web of Science
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Download PDF pdficon (637 KB) | Citation | Downloads: 710 | Views: 5,517

Author keywords
Network-on-Chip, Semi Markov process, modeling, queuing theory, simulation

References keywords
chip(12), network(11), design(11), systems(8), performance(8), model(6), networks(5), router(4), marculescu(4), circuits(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2012-11-30
Volume 12, Issue 4, Year 2012, On page(s): 19 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2012.04003
Web of Science Accession Number: 000312128400003
SCOPUS ID: 84872775158

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In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design.

References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [SCOPUS Times Cited 72]

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[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 3]

References Weight

Web of Science® Citations for all references: 866 TCR
SCOPUS® Citations for all references: 1,401 TCR

Web of Science® Average Citations per reference: 33 ACR
SCOPUS® Average Citations per reference: 54 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2022-05-16 17:04 in 112 seconds.

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Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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