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A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer ArchitectureWANG, J. , LI, Y. , LI, H.
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Network-on-Chip, Semi Markov process, modeling, queuing theory, simulation
chip(12), network(11), design(11), systems(8), performance(8), model(6), networks(5), router(4), marculescu(4), circuits(4)
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About this article
Date of Publication: 2012-11-30
Volume 12, Issue 4, Year 2012, On page(s): 19 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2012.04003
Web of Science Accession Number: 000312128400003
SCOPUS ID: 84872775158
In this paper, a performance analytical strategy is proposed for Network-on-Chip router with input buffer architecture. First, an analytical model is developed based on semi-Markov process. For the non-work-conserving router with small buffer size, the model can be used to analyze the schedule delay and the average service time for each buffer when given the related parameters. Then, the packet average delay in router is calculated by using the model. Finally, we validate the effectiveness of our strategy by simulation. By comparing our analytical results to simulation results, we show that our strategy successfully captures the Network-on-Chip router performance and it performs better than the state-of-art technology. Therefore, our strategy can be used as an efficiency performance analytical tool for Network-on-Chip design.
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