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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
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ROMANIA

Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  1/2013 - 2

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

HOO, C.-S. See more information about HOO, C.-S. on SCOPUS See more information about HOO, C.-S. on IEEExplore See more information about HOO, C.-S. on Web of Science, JEEVAN, K. See more information about  JEEVAN, K. on SCOPUS See more information about  JEEVAN, K. on SCOPUS See more information about JEEVAN, K. on Web of Science, GANAPATHY, V. See more information about  GANAPATHY, V. on SCOPUS See more information about  GANAPATHY, V. on SCOPUS See more information about GANAPATHY, V. on Web of Science, RAMIAH, H. See more information about RAMIAH, H. on SCOPUS See more information about RAMIAH, H. on SCOPUS See more information about RAMIAH, H. on Web of Science
 
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Download PDF pdficon (565 KB) | Citation | Downloads: 960 | Views: 3,503

Author keywords
design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization

References keywords
design(14), systems(12), floorplanning(12), vlsi(8), representation(6), circuits(6), algorithm(6), aided(6), scale(5), optimization(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-02-28
Volume 13, Issue 1, Year 2013, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.01002
Web of Science Accession Number: 000315768300002
SCOPUS ID: 84875343057

Abstract
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Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.


References | Cited By  «-- Click to see who has cited this paper

[1] J. M. Lin, Y. W. Chang, and S. P. Lin, "Corner sequence-A p-admissible floorplan representation with a worst case linear-time packing scheme," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 4, pp. 8-12, 2003.
[CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 39]


[2] J. Liu, W. C. Zhong, L. C. Jiao, and X. Li, "Moving block sequence and organizational evolutionary algorithm for general floorplanning with arbitrarily shaped rectilinear blocks," IEEE Transactions on Evolutionary Computation, vol. 12, no. 5, pp. 630-646, 2008.
[CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 32]


[3] S. N. Adya, and I. L. Markov, "Fixed-outline floorplanning: enabling hierarchical design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1120-1135, 2003.
[CrossRef] [Web of Science Times Cited 219] [SCOPUS Times Cited 306]


[4] J. Cong, M. Romesis, and J. R. Shinnerl, "Fast floorplanning by look-ahead enabled recursive bipartitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1719-1732, 2006.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 37]


[5] J. M. Lin, and Z. X. Hung, "UFO: Unified convex optimization algorithm for fixed-outline floorplanning considering pre-placed modules," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 7, pp. 1034-1044, 2011.
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 15]


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[CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 19]


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[CrossRef]


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[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 4]


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[CrossRef] [Web of Science Times Cited 921] [SCOPUS Times Cited 1165]


[12] P. N. Guo, T. Takahashi, C. K. Cheng, and T. Yoshimura, "Floorplanning using a tree representation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 281-289, 2001.
[CrossRef] [Web of Science Times Cited 59] [SCOPUS Times Cited 77]


[13] Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu, "B*-trees: A new representation for nonslicing floorplans," in Proceedings of Design Automation Conference, 2000, pp. 458-463. [CiteSeerX]

[14] X. Hong, G. Huang, Y. Cai, S. Dong, C. K. Cheng, and J. Gu, "Corner block list representation and its application to floorplan optimization," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 51, no. 5, pp. 228-233, 2004.
[CrossRef] [Web of Science Times Cited 42] [SCOPUS Times Cited 47]


[15] J. M. Lin, and Y. W. Chang, "TCG: A transitive closure graph-based representation for nonslicing floorplans," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 2, pp. 288-292, 2005.
[CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 39]


[16] J. G. Kim, and Y. D. Kim, "A linear programming-based algorithm for floorplanning in VLSI design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 584-592, 2003.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 40]


[17] C. Luo, M. F. Anjos, and A. Vannelli, "Large-scale fixed-outline floorplanning design using convex optimization techniques," in Proceedings of Asia and South Pacific Design Automation Conference, 2008, pp. 198-203.

[18] S. Alupoaei, and S. Katoori, "Ant Colony System application to macrocell overlap removal," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1118-1123, 2004.
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 28]


[19] A. Colorni, M. Dorigo, and V. Maniezzo, "Distributed optimization by ant colonies," in European Conference on Artificial Intelligence, 1991, pp. 134-142.

[20] C.-S. Hoo, H.-C. Yeo, K. Jeevan, V. Ganapathy, H. Ramiah, I.A. Badruddin, "Hierarchical Congregated Ant System for Bottom-up VLSI Placements," Engineering Applications of Artificial Intelligence, vol. 26, no. 1, pp. 584-602, 2013.
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 10]


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[22] J. Rabaey, Gigabyte systems research center 2005.

[23] Y. Pang, C. K. Cheng, and T. Yoshimura, "An enhanced perturbing algorithm for floorplan design using the O-tree representation," in Proceedings of International Symposium on Physical Design, 2000, pp.168-173.
[CrossRef] [SCOPUS Times Cited 62]


[24] G. L. Chen, W. Z. Guo, and Y. Z. Chen, "A PSO-based intelligent decision algorithm for VLSI floorplanning," Soft Computing-A Fusion of Foundations, Methodologies and Applications, vol. 14, no. 12, pp. 1329-1337, 2009.
[CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 67]


[25] J. Chen, and J. Chen, "A hybrid evolution algorithm for VLSI floorplanning," International Conference on Computational Intelligence and Software Engineering, 2010, pp. 1-4.
[CrossRef] [SCOPUS Times Cited 7]




References Weight

Web of Science® Citations for all references: 1,491 TCR
SCOPUS® Citations for all references: 2,008 TCR

Web of Science® Average Citations per reference: 57 ACR
SCOPUS® Average Citations per reference: 77 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2022-09-23 06:03 in 124 seconds.




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