|2/2013 - 1|
Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)CUEVAS-FARFAN, E. , MORALES-SANDOVAL, M. , MORALES-REYES, A. , FEREGRINO-URIBE, C. , ALGREDO-BADILLO, I. , KITSOS, P. , CUMPLIDO, R.
|View the paper record and citations in|
|Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science|
|Download PDF (1,421 KB) | Citation | Downloads: 1,358 | Views: 18|
data security, cryptography, public key, algorithm design and analysis, field programmable gate arrays
karatsuba(12), systems(6), reconfigurable(6), ofman(6), efficient(6), multipliers(5), multiplication(5), reduction(4), parallel(4), multiplier(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2013-05-31
Volume 13, Issue 2, Year 2013, On page(s): 3 - 10
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.02001
Web of Science Accession Number: 000322179400001
SCOPUS ID: 84878919037
In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.
|References|||||Cited By «-- Click to see who has cited this paper|
| B. Schneier, Applied Cryptography, 2nd edition. Wiley, 1996, p. 758.
 A. Karatsuba and Y. Ofman, "Multiplication of Multidigit Numbers on Automata," Soviet Physics-Doklady, vol. 7, no. 7, pp. 595-596, 1963.
 M. Knezevic, F. Vercauteren, and I. Verbauwhede, "Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods," IEEE Transactions on Computers, vol. 59, no. 12, pp. 1715-1721, Dec. 2010.
[CrossRef] [Web of Science Times Cited 26] [SCOPUS Times Cited 41]
 G. X. Yao, J. Fan, R. C. C. Cheung, and I. Verbauwhede, "A High Speed Pairing Coprocessor Using RNS and Lazy Reduction," IACR Cryptology ePrint Archive, vol. 2011, p. 258, 2011.
 A. B. El-sisi, S. M. Shohdy, and N. Ismail, "Reconfigurable Implementation of Karatsuba Multiplier for Galois Field in Elliptic Curves," Novel Algorithms and Techniques in Telecommunications and Networking, pp. 97-92, 2010.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]
 H. Fan, J. Sun, M. Gu, and K.-Y. Lam, "Overlap-free Karatsuba-Ofman polynomial multiplication algorithms," IET Information Security, vol. 4, no. 1, p. 8, 2010.
[CrossRef] [Web of Science Times Cited 49] [SCOPUS Times Cited 55]
 G. Zhou, H. Michalik, and L. Hinsenkamp, "Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 1057-1066, Jul. 2010.
[CrossRef] [Web of Science Times Cited 30] [SCOPUS Times Cited 40]
 M. Machhout, M. Zeghid, W. El Hadj Youssef, B. Bouallegue, A. Baganne, and R. Tourki, "Efficient Large Numbers Karatsuba-Ofman Multiplier Designs for Embedded Systems," in Conference of the World Academy of Science Engineering and Technology 28, 2009, pp. 992-1001.
 G. Zhou, H. Michalik, and L. Hinsenkamp, "Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs," Reconfigurable Computing: Architectures, Tools and Applications, vol. 5453, pp. 193-203, 2009.
[CrossRef] [SCOPUS Times Cited 36]
 W. El hadj youssef, M. Machhout, M. Zeghid, B. Bouallegue, and R. Tourki, "Efficient hardware architecture of recursive Karatsuba-Ofman multiplier," in 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008, pp. 1-6.
 Y. L. Zhang, G. C. Shou, Y. H. Hu, and Z. G. Guo, "Low Complexity GF(2m) Multiplier Based on Iterative Karatsuba Algorithm," Advanced Materials Research, vol. 546-547, pp. 1409-1414, Jul. 2012.
[CrossRef] [SCOPUS Times Cited 1]
 A. Weimerskirch and C. Paar, "Generalizations of the Karatsuba Algorithm for Efficient Implementations," Cryptology ePrint Archive, vol. 2006/224, 2006. [CiteSeerX]
 J. von zur Gathen and J. Shokrollahi, "Efficient FPGA-Based Karatsuba Multipliers for Polynomials over F2," Selected Areas in Cryptography, vol. 3897, pp. 359-369, 2006.
[CrossRef] [SCOPUS Times Cited 40]
 N. S. Chang, C. H. Kim, Y.-H. Park, and J. Lim, "A Non-redundant and Efficient Architecture for Karatsuba-Ofman Algorithm," Information Security, vol. 3650, pp. 288-299, 2005.
[CrossRef] [SCOPUS Times Cited 10]
 N. A. Saqib, F. Rodriguez-Henriquez, and A. Diaz-Perez, "A parallel architecture for fast computation of elliptic curve scalar multiplication over GF(2m)," in 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., 2004, vol. 00, no. C, pp. 144-151.
 M. Ernst, M. Jung, F. Madlener, S. A. Huss, and R. Bl, "A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n)," in Cryptographic Hardware and Embedded Systems - CHES 2002, vol. 2523, B. Kaliski, C. Koc, and C. Paar, Eds. Springer Berlin / Heidelberg, 2003, pp. 381-399. [CiteSeerX]
 F. Rodriguez-Henriquez and C. K. Koc, "On Fully Parallel Karatsuba Multipliers for GF(2m)," in Computer Science and Technology 2003, 2003. [CiteSeerX]
 M. Jung, F. Madlener, M. Ernst, and S. A. Huss, "A Reconfigurable Coprocessor for Finite Field Multiplication in GF(2m)," in IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip (HRSoc'02), 2002. [CiteSeerX]
 M. Morales-Sandoval, C. Feregrino-Uribe, and P. Kitsos, "Bit-serial and digit-serial GF(2m) Montgomery multipliers using linear feedback shift registers," IET Computers & Digital Techniques, vol. 5, no. 2, p. 86, 2010.
[CrossRef] [Web of Science Times Cited 26] [SCOPUS Times Cited 30]
 J. von zur Gathen and J. Gerhard, "Arithmetic and factorization of polynomial over (extended abstract)," in Proceedings of the 1996 international symposium on Symbolic and algebraic computation - ISSAC '96, 1996, pp. 1-9.
 D. G. Cantor, "On arithmetical algorithms over finite fields," Journal of Combinatorial Theory, vol. 50, no. 2, pp. 285 - 300, 1989.
[CrossRef] [Web of Science Times Cited 45] [SCOPUS Times Cited 54]
 M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, 1st ed. WILEY-IEEE PRESS, 1994.
[CrossRef] [SCOPUS Times Cited 23]
 M. M. Knezevic, K. Sakiyama, J. Fan, and I. Verbauwhede, "Modular Reduction in GF(2m) without Precomputational Phase," in International Workshop on the Arithmetic of Finite Fields (WAIFI 2008), 2008, vol. 5130, pp. 77-87.
[CrossRef] [SCOPUS Times Cited 21]
 C. K. Koc, "Montgomery reduction with even modulus," IEE Proceedings of Computers and Digital Techniques, vol. 141, no. 2, pp. 314-316, 2010.
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 12]
 F. Rodriguez-Henriquez, A. Diaz-Perez, N. A. Saqib, and C. K. Koc, Cryptographic Algorithms on Reconfigurable Hardware. Boston, MA: Springer US, 2006.
 "FIPS PUB 186-3 Digital Signature Standard (DSS)," NIST - Federal Information Processing Standars Publication, 2009.
Web of Science® Citations for all references: 187 TCR
SCOPUS® Citations for all references: 364 TCR
Web of Science® Average Citations per reference: 7 ACR
SCOPUS® Average Citations per reference: 13 ACR
TCR = Total Citations for References / ACR = Average Citations per Reference
We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more
Citations for references updated on 2022-08-04 21:12 in 88 seconds.
Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.