4/2013 - 15 |
Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule SelectionRAM, D. S. H. , BHUVANESWARI, M. C. , UMADEVI, S. |
Extra paper information in |
Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science |
Download PDF (613 KB) | Citation | Downloads: 1,156 | Views: 3,646 |
Author keywords
high level synthesis, field programmable gate arrays, power dissipation, genetic algorithms, reconfigurable logic
References keywords
power(11), design(10), vlsi(9), systems(8), optimization(7), level(7), high(7), integration(5), evolutionary(5), very(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 85 - 92
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04015
Web of Science Accession Number: 000331461300015
SCOPUS ID: 84890198448
Abstract
FPGAs are increasingly being used to implement data path intensive algorithms for signal processing and image processing applications. In High Level Synthesis of Data Flow Graphs targeted at FPGAs, the effect of interconnect resources such as multiplexers must be considered since they contribute significantly to the area and switching power. We propose a binding framework for behavioral synthesis of Data Flow Graphs (DFGs) onto FPGA targets with power reduction as the main criterion. The technique uses a multi-objective GA, NSGA II for design space exploration to identify schedules that have the potential to yield low-power bindings from a population of non-dominated solutions. A greedy constructive binding technique reported in the literature is adapted for interconnect minimization. The binding is further subjected to a perturbation process by altering the register and multiplexer assignments. Results obtained on standard DFG benchmarks indicate that our technique yields better power aware bindings than the constructive binding approach with little or no area overhead. |
References | | | Cited By «-- Click to see who has cited this paper |
[1] D. S. H. Ram, M. C. Bhuvaneswari, S. M. Logesh, "A novel evolutionary technique for multi-objective power, area and delay optimization in high level synthesis of datapaths," IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp.290-295, 2011 [CrossRef] [Web of Science Times Cited 18] [SCOPUS Times Cited 21] [2] D. S. Harish Ram, M. C. Bhuvaneswari, Shanthi S. Prabhu, "A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths, VLSI Design journal, vol 2012. [CrossRef] [Web of Science Times Cited 12] [SCOPUS Times Cited 30] [3] K. Deb, A. Pratap, S. Agarwal, T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE Transactions on Evolutionary Computation, vol.6, no.2, pp.182-197, 2002 [CrossRef] [Web of Science Times Cited 31183] [SCOPUS Times Cited 39158] [4] K. Deb, "Multi-objective optimization using evolutionary algorithms," John Wiley and Sons, 2003 [5] V. Krishnan, S. Katkoori, A genetic algorithm for the design space exploration of datapaths during high-level Synthesis," IEEE Transactions on Evolutionary Computation, vol.10, no.3, pp. 213- 229 2006 [CrossRef] [Web of Science Times Cited 61] [SCOPUS Times Cited 103] [6] E. Casseau, B. Le Gal, "High-level synthesis for the design of FPGA-based signal processing systems," International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS'09, pp.25-32, 2009 [7] C. Y. Huang, Y. S. Chen, Y. L. Lin, Y. C. Hsu, "Data path allocation based on bipartite weighted matching," Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC '90, pp 499-504, 1990 [CrossRef] [8] Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose, "GABIND: A GA approach to allocation and binding for the high-level synthesis of data paths," Very Large Scale Integration (VLSI) Systems, vol 8 no. 6, pp 747-750, 2000 [9] X. Tang, T. Jiang, A. Jones, and P. Banerjee, "Behavioral synthesis of data-dominated circuits for minimal energy implementation," Proceedings of the International Conference on VLSI Design, pp 267-273, 2005. [10] N. Chabini, W. Wolf, "Unification of scheduling, binding and retiming to reduce power consumption under timings and resources constraints," Very Large Scale Integration (VLSI) Systems, vol.13, no. 10, pp. 1113-1126, 2005. [11] A. K. Murugavel, N. Ranganathan, "A game theoretic approach for power optimization during behavioral synthesis," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1031-1043, 2003. [CrossRef] [Web of Science Times Cited 17] [SCOPUS Times Cited 20] [12] D. Chen, J. Cong, Y. Fan, L. Wan, "LOPASS: A Low-power architectural synthesis system for FPGAs with interconnect estimation and optimization," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.4, pp.564-577, 2010 [CrossRef] [Web of Science Times Cited 25] [SCOPUS Times Cited 42] [13] A. A. Del Barrio, S. O. Memik, M. C. Molina, J. M. Mendias, R. Hermida, "A fragmentation aware high-level synthesis flow for low power heterogeneous datapaths," Integration, the VLSI journal, [CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 2] [14] D. Bekiaris, E. S. Xanthopoulos, G. Economakos, D. Soudris, "Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments," International workshop on communication centric system on chip ReCoSoC, pp 1-8, 2012 [15] D. Bekiaris, G. Economakos, E.S. Xanthopoulos, D. Soudris, "Low-power reconfigurable component utilization in a high-level synthesis flow," International Conference on Reconfigurable computing and FPGAs, pp 428-433, 2011 [16] C. Wolinski, K. Kuchcinski, E. Raffin, F. Charot, "Architecture-driven synthesis of reconfigurable cells," Euromicro conference on digital system design/architecture, methods and tools, pp 531-538, 2009 [17] R. Tessier, "Power-efficient RAM mapping algorithms for FPGA embedded memory blocks," IEEE Transactions on CAD of Integrated Circuits and Systems, vol 26, no.2, 2007 [18] F. Ferrandi, P. L. Lanzi, G. Palermo, C. Pilato, D. Sciuto, A. Tumeo, "An evolutionary approach to area-time optimization of FPGA designs," International Conference on Embedded Systems: Architectures, Modeling and Simulation, IC-SAMOS, pp 145-152, , 2007 [19] J. M. Chang, M. Pedram, "Register allocation and binding for low power," Proceedings of ACM/IEEE Design Automation Conference, DAC '95, pp 29-35, 1995 [20] E. Kursun, R. Mukherjee, S. O. Memik," Early quality assessment for low power behavioral synthesis. Journal of Low Power Electronics, vol 1, no.3, pp 1-13, 2005 [CrossRef] [Web of Science Record] [21] S. H. Gerez, "Algorithms for VLSI design automation, John Wiley and Sons, 2000 [22] D. Chen, J. Cong, "Register binding and port assignment for multiplexer optimization. In: ASP-DAC '04 Proceedings of the 2004 Asia and South Pacific Design Automation Conference, pp. 68-73, 2004 [23] R. K. Ahuja, T. L. Magnanti, J.B. Orlin, "Network Flows: Theory, Algorithms, and Applications," Prentice-Hall, Englewood Cliffs, NJ, 1993. [24] Mediabench benchmark suite Available [Online] Available: Temporary on-line reference link removed - see the PDF document [25] Xpower estimator user guide [Online] Available: Temporary on-line reference link removed - see the PDF document Web of Science® Citations for all references: 31,317 TCR SCOPUS® Citations for all references: 39,376 TCR Web of Science® Average Citations per reference: 1,205 ACR SCOPUS® Average Citations per reference: 1,514 ACR TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-11-30 17:50 in 63 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. Note2: SCOPUS® is a registered trademark of Elsevier B.V. Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site. |
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.