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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
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ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  4/2013 - 3

 HIGHLY CITED PAPER 

A Cell Sizing Technique for Mitigating Logic Soft Errors in Gate-level Designs

PARK, J. K. See more information about PARK, J. K. on SCOPUS See more information about PARK, J. K. on IEEExplore See more information about PARK, J. K. on Web of Science, KIM, J. T. See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on SCOPUS See more information about KIM, J. T. on Web of Science
 
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Download PDF pdficon (846 KB) | Citation | Downloads: 881 | Views: 4,072

Author keywords
single event transient, soft error, soft error mitigation, gate-level, gate sizing, cell sizing

References keywords
soft(16), error(15), design(9), circuits(6), combinational(5), analysis(5), systems(4), rate(4), logic(4), designs(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-11-30
Volume 13, Issue 4, Year 2013, On page(s): 13 - 18
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.04003
Web of Science Accession Number: 000331461300003
SCOPUS ID: 84890160731

Abstract
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The effect of logic soft errors on the degradation of the reliability becomes more crucial in the case of nano-meter semiconductor designs. Several hardening techniques have been reported from the transistor- to system-level. In order to suppress the single event transients originating from logic gates, this paper presents an improved heuristic search utilizing the gate-sizing technique. The algorithm re-orders the gate-traversal to maintain the reduced soft error rates of the preceding logic gates. The preferential candidates for the two successive algorithms are the logic gates near the primary outputs and flip-flops, rather than those of the higher portions of block soft error rate. The proposed technique reduces the logic soft error rate by more than 60% compared to the existing method in 45nm CMOS cell designs.


References | Cited By  «-- Click to see who has cited this paper

[1] A. Dixit and A. Wood, "The Impact of New Technology on Soft Error Rates," IEEE Int. Reliability Physics Symposium, pp.5B4.1-5B4.7, 2011.
[CrossRef] [SCOPUS Times Cited 254]


[2] E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo and T. Toba, "Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule," IEEE Trans. On Electron Devices, Vol.57, No.7, pp.1527-1537, 2010.
[CrossRef] [Web of Science Times Cited 337] [SCOPUS Times Cited 424]


[3] C. Slayman, "Soft error trends and mitigation techniques in memory devices," proc. of Reliability and Maintainability Symposium, pp.1-5, 2011.
[CrossRef] [SCOPUS Times Cited 42]


[4] J. L. Leray, "Effects of atmospheric neutrons on devices, at sea level and in avionics embedded systems," Microelectronics Reliability, Vol.47 pp.1827-1835, 2007.

[5] W. Sootkaneung, K. K. Saluja, "Soft error reduction through gate input dependent weighted sizing in combinational circuits," proc. of Int. Symposium on Quality Electronic Design, pp.1-8, 2011.
[CrossRef] [SCOPUS Times Cited 13]


[6] L. Xiao, W. Sheng and Z. Mao, "Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm," proc. of Design Automation Conference, pp.502-507, 2009.

[7] J. K. Park and J. T. Kim, "A soft error mitigation technique for constrained gate-level designs," IEICE Electronics Express, Vol.5, No.18, pp.698-704, 2008.

[8] N. M. Zivanov and D. Marculescu, "MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits," proc. of Design Automation Conference, pp.767-772, 2006.

[9] Q. Zhou and K. Mohanram, "Cost-Effective Radiation Hardening Technique for Combinational Logic," Int. conf. on Computer Aided Design, 2004.
[CrossRef] [Web of Science Times Cited 59]


[10] H. Asadi and M. Tahoori, "Soft error hardening for logic-level designs," proc. of ISCAS, 2006.
[CrossRef]


[11] Y. S. Dhillon, A. U. Diril, A. Chatterjee, A. D. Singh, "Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance," IEEE Trans. on Very Large Scale Integration Systems Vol.14, No.5, pp.514-524, 2006.
[CrossRef] [Web of Science Times Cited 57] [SCOPUS Times Cited 77]


[12] W. Kai-Chiang and D. Marculescu, "soft error rate reduction using redundancy addition and removal," proc. of ASPDAC, pp.559-564, 2008.
[CrossRef] [SCOPUS Times Cited 25]


[13] J. K. Park, H. S. Choi and J. T. Kim, "A Soft Error Analysis Tool for High-Speed Digital Designs," proc. of 2nd Int. conf. on Ubiquitous Information Management and Communication, pp.280-282, 2008.

[14] R. R. Rao, K. Chopra and D. T. Blaauw, "Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems Vol.26, No.3, 2007.
[CrossRef] [Web of Science Times Cited 79] [SCOPUS Times Cited 98]


[15] B. Zhang, W. Wang and M. Orshansky, "FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs," 7th Int. Symposium on Quality Electronic Design, pp.755-760, 2006.
[CrossRef] [SCOPUS Times Cited 153]


[16] NANGATE, 45nm Open Cell Library 4th Release, 2009. [Online]. Available: http://www.nangate.com.

[17] P. Hazucha and C. Svensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans. on Nuclear Science, Vol.47, No.6, pp. 2586-2594, 2000.
[CrossRef] [Web of Science Times Cited 386] [SCOPUS Times Cited 478]


[18] M. Zhang and N. R. Shanbhag, "Soft-Error-Rate-Analysis (SERA) Methodology," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.25, No.10, pp.2140-2155, 2006.
[CrossRef] [Web of Science Times Cited 95] [SCOPUS Times Cited 119]


[19] J. F. Ziegler, "Terrestrial cosmic rays," IBM J., Vol.40, No.1, pp.19-39, 1996.

[20] R. Rajaraman, J. S. Kim, N. Vijaykarishnan, Y. Xie and M. J. Irwin, "SEAT-LA: A Soft Error Analysis Tool for Combinational Logic," Proc. of 19th Int. Conf. on VLSI Design, pp.499-502, 2006.
[CrossRef] [SCOPUS Times Cited 153]




References Weight

Web of Science® Citations for all references: 1,013 TCR
SCOPUS® Citations for all references: 1,836 TCR

Web of Science® Average Citations per reference: 48 ACR
SCOPUS® Average Citations per reference: 87 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-07-14 00:07 in 89 seconds.




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