Click to open the HelpDesk interface
AECE - Front page banner

Menu:


FACTS & FIGURES

JCR Impact Factor: 0.825
JCR 5-Year IF: 0.752
SCOPUS CiteScore: 2.5
Issues per year: 4
Current issue: Aug 2022
Next issue: Nov 2022
Avg review time: 74 days
Avg accept to publ: 48 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


TRAFFIC STATS

1,976,095 unique visits
789,717 downloads
Since November 1, 2009



Robots online now
PetalBot
Sogou
bingbot


SCOPUS CiteScore

SCOPUS CiteScore


SJR SCImago RANK

SCImago Journal & Country Rank




TEXT LINKS

Anycast DNS Hosting
MOST RECENT ISSUES

 Volume 22 (2022)
 
     »   Issue 3 / 2022
 
     »   Issue 2 / 2022
 
     »   Issue 1 / 2022
 
 
 Volume 21 (2021)
 
     »   Issue 4 / 2021
 
     »   Issue 3 / 2021
 
     »   Issue 2 / 2021
 
     »   Issue 1 / 2021
 
 
 Volume 20 (2020)
 
     »   Issue 4 / 2020
 
     »   Issue 3 / 2020
 
     »   Issue 2 / 2020
 
     »   Issue 1 / 2020
 
 
 Volume 19 (2019)
 
     »   Issue 4 / 2019
 
     »   Issue 3 / 2019
 
     »   Issue 2 / 2019
 
     »   Issue 1 / 2019
 
 
  View all issues  








LATEST NEWS

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2021 is 2.5, the same as for 2020 but better than all our previous results.

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

2021-Jun-06
SCOPUS published the CiteScore for 2020, computed by using an improved methodology, counting the citations received in 2017-2020 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2020 is 2.5, better than all our previous results.

2021-Apr-15
Release of the v3 version of AECE Journal website. We moved to a new server and implemented the latest cryptographic protocols to assure better compatibility with the most recent browsers. Our website accepts now only TLS 1.2 and TLS 1.3 secure connections.

Read More »


    
 

  1/2014 - 3

Adaptive Neuro-fuzzy Inference System as Cache Memory Replacement Policy

CHUNG, Y. M. See more information about CHUNG, Y. M. on SCOPUS See more information about CHUNG, Y. M. on IEEExplore See more information about CHUNG, Y. M. on Web of Science, HALIM, Z. A. See more information about HALIM, Z. A. on SCOPUS See more information about HALIM, Z. A. on SCOPUS See more information about HALIM, Z. A. on Web of Science
 
View the paper record and citations in View the paper record and citations in Google Scholar
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (723 KB) | Citation | Downloads: 775 | Views: 3,505

Author keywords
cache memory, fuzzy neural networks, Takagi-Sugeno model, replacement policy, supervised learning

References keywords
cache(12), fuzzy(10), systems(8), replacement(7), system(6), policies(5), performance(5), adaptive(5), neuro(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-02-28
Volume 14, Issue 1, Year 2014, On page(s): 15 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.01003
Web of Science Accession Number: 000332062300003
SCOPUS ID: 84894609777

Abstract
Quick view
Full text preview
To date, no cache memory replacement policy that can perform efficiently for all types of workloads is yet available. Replacement policies used in level 1 cache memory may not be suitable in level 2. In this study, we focused on developing an adaptive neuro-fuzzy inference system (ANFIS) as a replacement policy for improving level 2 cache performance in terms of miss ratio. The recency and frequency of referenced blocks were used as input data for ANFIS to make decisions on replacement. MATLAB was employed as a training tool to obtain the trained ANFIS model. The trained ANFIS model was implemented on SimpleScalar. Simulations on SimpleScalar showed that the miss ratio improved by as high as 99.95419% and 99.95419% for instruction level 2 cache, and up to 98.04699% and 98.03467% for data level 2 cache compared with least recently used and least frequently used, respectively.


References | Cited By  «-- Click to see who has cited this paper

[1] H. Ghasemzadeh, et al., "Modified pseudo LRU replacement algorithm," in Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems, pp. 370-376, 2006.
[CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 22]


[2] W. A. Wong and J. L. Baer, "Modified LRU policies for improving second-level cache behavior," in Sixth International Symposium on High-Performance Computer Architecture, pp. 49-60, 2000.
[CrossRef]


[3] S. Gupta, et al., "Locality Principle Revisited: A Probability-Based Quantitative Approach," in IEEE 26th International Parallel & Distributed Processing Symposium (IPDPS), pp. 995-1009, 2012.
[CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 15]


[4] L. Donghee, et al., "LRFU: a spectrum of policies that subsumes the least recently used and least frequently used policies," IEEE Transactions on Computers, vol. 50, pp. 1352-1361, 2001.
[CrossRef] [Web of Science Times Cited 290] [SCOPUS Times Cited 401]


[5] M. K. Qureshi, et al., "Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching," IEEE Micro, vol. 28, pp. 91-98, 2008.
[CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 12]


[6] S. Kaxiras, et al., "Cache decay: exploiting generational behavior to reduce cache leakage power," in 28th Annual International Symposium on Computer Architecture, pp. 240-251, 2001.
[CrossRef] [Web of Science Times Cited 47] [SCOPUS Times Cited 96]


[7] L. An-Chow, et al., "Dead-block prediction & dead-block correlating prefetchers," in 28th Annual International Symposium on Computer Architecture, pp. 144-154, 2001.
[CrossRef] [Web of Science Times Cited 118]


[8] M. Atique and M. S. Ali, "An Adaptive Neuro Fuzzy Inference System for Cache Replacement in Multimedia Operating System," in International Conference on Electrical and Computer Engineering, 2006 (ICECE '06). pp. 286-290, 2006.
[CrossRef] [SCOPUS Times Cited 2]


[9] O. Hammami, "Pipeline integration of neuro and fuzzy cache management techniques," in Proceedings of the Sixth IEEE International Conference on Fuzzy Systems, vol.2, pp. 653-658, 1997.
[CrossRef]


[10] W. Ali and S. M. Shamsuddin, "Neuro-fuzzy system in web client-side caching," in Expert Systems with Applications, vol. 38, no. 12, pp. 14715-14725, 2011.
[CrossRef] [Web of Science Times Cited 17] [SCOPUS Times Cited 22]


[11] M. S. Obaidat and H. Khalid, "Estimating neural networks-based algorithm for adaptive cache replacement," IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, vol. 28, pp. 602-611, 1998.
[CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 11]


[12] K. Sedigheh, et al., "A Fuzzy Cache Replacement Policy and Its Experimental Performance Assessment," in Innovations in Information Technology, pp. 1-5, 2006.
[CrossRef] [SCOPUS Times Cited 3]


[13] J. S. R. Jang, "ANFIS: adaptive-network-based fuzzy inference system," IEEE Transactions on Systems, Man and Cybernetics, vol. 23, pp. 665-685, 1993.
[CrossRef] [Web of Science Times Cited 9876] [SCOPUS Times Cited 12514]


[14] JANG, J. S. R. & SUN, C. T. "Neuro-fuzzy modeling and control," Proceedings of the IEEE, vol. 83, no. 3, pp. 378-406, 1995.
[CrossRef] [Web of Science Times Cited 1418] [SCOPUS Times Cited 1875]


[15] J. S. R. Jang, "Input selection for ANFIS learning," in Proceedings of the Fifth IEEE International Conference on Fuzzy Systems, 1996, vol.2, pp. 1493-1499
[CrossRef] [Web of Science Times Cited 184]


[16] T. Austin, et al., "SimpleScalar: An infrastructure for computer system modeling," Computer, vol. 35, pp. 59-67, 2002.
[CrossRef]


[17] K. Ganesan, et al., "Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics," Computer Performance Evaluation and Benchmarking, pp. 121-137, 2009.
[CrossRef] [SCOPUS Times Cited 13]


[18] A. A. Nair and L. K. John, "Simulation points for SPEC CPU 2006," in IEEE International Conference on Computer Design, pp. 397-403, 2008.
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 30]


[19] R. Gupta and S. Tokekar, "Efficient Pair of Replacement Algorithms for L1 and L2 Cache for Matrix Multiplication," in IEEE International Advance Computing Conference, 2009. (IACC 2009), pp. 502-507, 2009.
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 1]


[20] Z. Yuanyuan, et al., "Second-level buffer cache management," IEEE Transactions on Parallel and Distributed Systems, vol. 15, pp. 505-519, 2004.
[CrossRef] [Web of Science Times Cited 70] [SCOPUS Times Cited 116]


[21] M. Chaudhuri, "Pseudo-LIFO: The foundation of a new family of replacement policies for last-level caches," in 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 401-412, 2009.
[CrossRef] [SCOPUS Times Cited 78]


[22] L. Zhan-sheng, et al., "CRFP: A Novel Adaptive Replacement Policy Combined the LRU and LFU Policies," in IEEE 8th International Conference on Computer and Information Technology Workshops, pp. 72-79, 2008.
[CrossRef] [SCOPUS Times Cited 20]


[23] M. S. Haque, et al., "CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 126-133, 2011.
[CrossRef] [SCOPUS Times Cited 9]


[24] A. Milenkovic, et al., "A performance evaluation of memory hierarchy in embedded systems," in Proceedings of the 35th Southeastern Symposium on System Theory, pp. 427-431, 2003.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 9]


[25] Z. Qingbo and Z. Yuanyuan, "Power-aware storage cache management," IEEE Transactions on Computers, vol. 54, pp. 587-602, 2005.
[CrossRef] [SCOPUS Times Cited 97]




References Weight

Web of Science® Citations for all references: 12,080 TCR
SCOPUS® Citations for all references: 15,346 TCR

Web of Science® Average Citations per reference: 465 ACR
SCOPUS® Average Citations per reference: 590 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2022-09-25 02:59 in 152 seconds.




Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2022
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.




Website loading speed and performance optimization powered by: