Click to open the HelpDesk interface
AECE - Front page banner

Menu:


FACTS & FIGURES

JCR Impact Factor: 0.800
JCR 5-Year IF: 1.000
SCOPUS CiteScore: 2.0
Issues per year: 4
Current issue: Feb 2024
Next issue: May 2024
Avg review time: 54 days
Avg accept to publ: 60 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


TRAFFIC STATS

2,575,750 unique visits
1,023,293 downloads
Since November 1, 2009



Robots online now
SemanticScholar


SCOPUS CiteScore

SCOPUS CiteScore


SJR SCImago RANK

SCImago Journal & Country Rank




TEXT LINKS

Anycast DNS Hosting
MOST RECENT ISSUES

 Volume 24 (2024)
 
     »   Issue 1 / 2024
 
 
 Volume 23 (2023)
 
     »   Issue 4 / 2023
 
     »   Issue 3 / 2023
 
     »   Issue 2 / 2023
 
     »   Issue 1 / 2023
 
 
 Volume 22 (2022)
 
     »   Issue 4 / 2022
 
     »   Issue 3 / 2022
 
     »   Issue 2 / 2022
 
     »   Issue 1 / 2022
 
 
 Volume 21 (2021)
 
     »   Issue 4 / 2021
 
     »   Issue 3 / 2021
 
     »   Issue 2 / 2021
 
     »   Issue 1 / 2021
 
 
  View all issues  


FEATURED ARTICLE

Analysis of the Hybrid PSO-InC MPPT for Different Partial Shading Conditions, LEOPOLDINO, A. L. M., FREITAS, C. M., MONTEIRO, L. F. C.
Issue 2/2022

AbstractPlus






LATEST NEWS

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

Read More »


    
 

  1/2014 - 6

Design of Linear Systolic Arrays for Matrix Multiplication

MILOVANOVIC, E. I. See more information about MILOVANOVIC, E. I. on SCOPUS See more information about MILOVANOVIC, E. I. on IEEExplore See more information about MILOVANOVIC, E. I. on Web of Science, STOJCEV, M. K. See more information about  STOJCEV, M. K. on SCOPUS See more information about  STOJCEV, M. K. on SCOPUS See more information about STOJCEV, M. K. on Web of Science, MILOVANOVIC, I. Z. See more information about  MILOVANOVIC, I. Z. on SCOPUS See more information about  MILOVANOVIC, I. Z. on SCOPUS See more information about MILOVANOVIC, I. Z. on Web of Science, NIKOLIC, T. R. See more information about NIKOLIC, T. R. on SCOPUS See more information about NIKOLIC, T. R. on SCOPUS See more information about NIKOLIC, T. R. on Web of Science
 
View the paper record and citations in View the paper record and citations in Google Scholar
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (753 KB) | Citation | Downloads: 1,801 | Views: 5,487

Author keywords
address generator units, linear systolic arrays, matrix multiplication

References keywords
milovanovic(14), systolic(9), matrix(9), reconfigurable(5), multiplication(5), stojcev(4), processing(4), bekakos(4), arrays(4), array(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-02-28
Volume 14, Issue 1, Year 2014, On page(s): 37 - 42
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.01006
Web of Science Accession Number: 000332062300006
SCOPUS ID: 84894636997

Abstract
Quick view
Full text preview
This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs.


References | Cited By  «-- Click to see who has cited this paper

[1] J. Jang, S. Choi, V. K. Prasanna, "Area and time efficient implementations of matrix multiplication on FPGAs", In Proc. 1st IEEE International Conf. Field-Programmable Technology (ETP'02), Hong Kong, 2002, pp. 93-100.
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 51]


[2] A. Amira, P. Bouridane, A. Milligan, "Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing", In Proc. 11th International Conf. Field- Programmable Logic Appl. (FPL'01), Sidney, Australia, 2001, pp. 101-111.

[3] F. Bensaali, A. Amira, A. Bouridane, " Accelerating matrix product on reconfigurable hardware for image processing applications", IEE Proceedings -- Circuits, Devices and Systems, Vol. 152, No 3, pp. 236-246, june 2005.
[CrossRef] [Web of Science Times Cited 22] [SCOPUS Times Cited 30]


[4] L. Jianwen, J.C. Chuen, "Partially reconfigurable matrix multiplication for area and time efficiency on FPGAs", In Proc. 8th Euromicro Symp. Digital System Design (DSD2004), Renes, France, 2004, pp. 244- 248.

[5] P. Zicari, P. Corsonello, S. Perri, G. Cocorullo, "A matrix product accelerator for field programmable systems on chip", Microprocessors and Microsystems, Vol. 32, No 2, pp. 53-67, March 2008.
[CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 18]


[6] I. Z. Milovanovic, E. I. Milovanovic, B. M. Randjelovic, I. c. Jovanovic, "Matrix mutiplication on a bidirectional systolic arrays", FILOMAT, Vol. 17, No 1, pp. 135-141, 2003.
[CrossRef]


[7] D. I. Moldovan, "On the design of algorithms to VLSI systolic arrays", Proceedings of the IEEE, Vol. 71, No 1, pp. 113-120, 1983.
[CrossRef] [Web of Science Times Cited 175] [SCOPUS Times Cited 257]


[8] D. Grant, P. Denyer, I. Finlay, "Synthesis of address generators", In Proc IEEE Int. Conf. Computer Aided Design (ICCAD-89), Santa Clara, CA, 1989, pp. 116-119.

[9] H. T. Kung, "Why systolic architectures?", Computer, Vol. 15, No 1, pp. 37-46, January 1982.
[CrossRef] [SCOPUS Times Cited 1462]


[10] V. V. Voevodin, Mathematical models and methods in parallel processing, Nauka, Moscow, 1986 (In Russian).

[11] I. Z. Milovanovic, E. I. Milovanovic, M. P. Bekakos, "Synthesis of unidirectional systolic array for matrix-vector multiplication", Math. Comput. Modelling, Vol. 43, No 1-2, pp. 612-619, March 2006.
[CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 12]


[12] E. I. Milovanovic, M. P. Bekakos, I. Z. Milovanovic, "Synthesis of space optimal systolic arrays for band matrix-vector multiplication", J. Supercomputing, Vol. 49, No 3, pp. 269-290, September 2009.
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 2]


[13] M. P. Bekakos, I. Z. Milovanovic, E. I. Milovanovic, T. I. Tokic, M. K. Stojcev, Hexagonal systolic arrays for matrix multiplication, In: Highly Parallel Computations" Algorithms and Applications (M.P. Bekakos, ed.), Chapter 6, WIT Press, Southampton-Boston, 2001, 139-177.

[14] S. G. Sedukhin, "The Designing and Analysis of Systolic Algo- rithms and Structures", Programming, 2, pp. 20-40, 1991, (In Russian.)

[15] K. Compton, S. Hauck, "Reconfigurable computing: A syrvey of systems and software", ACM Comput. Surveys, Vol. 34, No 2, pp. 171-210, June 2002.
[CrossRef] [Web of Science Times Cited 647] [SCOPUS Times Cited 975]


[16] M. Hertz, R. Hartenstein, M. Miranda, E. Brockmeyer, F. Catthoor, "Memory Addressing Organization for Stream-based Reconfigurable Computing", Proc. IEEE ICECS 2002, Dubrovnik, Croatia, 2002, pp. 813-817.
[CrossRef] [SCOPUS Times Cited 22]


[17] G. Talavera, M. Jayapala, J. Carrabina, F. Catthoor, "Address generation optimization for embedded high-performance Processors: A Survey", J. Sign. Process. Syst., Vol. 53, No 3, pp. 271-284, December 2008.
[CrossRef] [Web of Science Times Cited 18] [SCOPUS Times Cited 24]


[18] E. I. Milovanovic, T. R. Nikolic, M. K. Stojcev, I. Z. Milovanovic, "Multi-functional systolic array with reconfgurable micro-power processing elements", Microelectron. Reliab., Vol. 49, No 7, pp. 813-820, July 2009.
[CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 8]


[19] M. K. Stojcev, I. Z. Milovanovic, E. I. Milovanovic, T. R. Nikolic, "Address generators for linear systolic array", Microelectron. Reliab., Vol. 50, No 2, pp. 292-303, February 2010.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 4]


[20] Embeded Development HW/SW kit, Spartan 3A DSP S3D1800A, MicroBlaze Processor Edition.

[21] I. Z. Milovanovic, M. K. Stojcev, E. I. Milovanovic, T. R. Nikolic, "Linear Processor array in DSP", Proc. 28th International Conference on Microelectronics (MIEL 2012), Nis, Serbia, 13-16 May, 2012, pp. 387-392, ISBN 978-1-4673-0236-4



References Weight

Web of Science® Citations for all references: 919 TCR
SCOPUS® Citations for all references: 2,865 TCR

Web of Science® Average Citations per reference: 42 ACR
SCOPUS® Average Citations per reference: 130 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-05-16 09:23 in 90 seconds.




Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2024
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.




Website loading speed and performance optimization powered by: 


DNS Made Easy