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Design of Linear Systolic Arrays for Matrix MultiplicationMILOVANOVIC, E. I.   , STOJCEV, M. K. , MILOVANOVIC, I. Z. , NIKOLIC, T. R. |
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Author keywords
address generator units, linear systolic arrays, matrix multiplication
References keywords
milovanovic(14), systolic(9), matrix(9), reconfigurable(5), multiplication(5), stojcev(4), processing(4), bekakos(4), arrays(4), array(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2014-02-28
Volume 14, Issue 1, Year 2014, On page(s): 37 - 42
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.01006
Web of Science Accession Number: 000332062300006
SCOPUS ID: 84894636997
Abstract
This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs. |
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| [1] J. Jang, S. Choi, V. K. Prasanna, "Area and time efficient implementations of matrix multiplication on FPGAs", In Proc. 1st IEEE International Conf. Field-Programmable Technology (ETP'02), Hong Kong, 2002, pp. 93-100. [CrossRef] [Web of Science Times Cited 21] [2] A. Amira, P. Bouridane, A. Milligan, "Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing", In Proc. 11th International Conf. Field- Programmable Logic Appl. (FPL'01), Sidney, Australia, 2001, pp. 101-111. [3] F. Bensaali, A. Amira, A. Bouridane, " Accelerating matrix product on reconfigurable hardware for image processing applications", IEE Proceedings -- Circuits, Devices and Systems, Vol. 152, No 3, pp. 236-246, june 2005. [CrossRef] [Web of Science Times Cited 22] [4] L. Jianwen, J.C. Chuen, "Partially reconfigurable matrix multiplication for area and time efficiency on FPGAs", In Proc. 8th Euromicro Symp. Digital System Design (DSD2004), Renes, France, 2004, pp. 244- 248. [5] P. Zicari, P. Corsonello, S. Perri, G. Cocorullo, "A matrix product accelerator for field programmable systems on chip", Microprocessors and Microsystems, Vol. 32, No 2, pp. 53-67, March 2008. [CrossRef] [Web of Science Times Cited 11] [6] I. Z. Milovanovic, E. I. Milovanovic, B. M. Randjelovic, I. c. Jovanovic, "Matrix mutiplication on a bidirectional systolic arrays", FILOMAT, Vol. 17, No 1, pp. 135-141, 2003. [CrossRef] [7] D. I. Moldovan, "On the design of algorithms to VLSI systolic arrays", Proceedings of the IEEE, Vol. 71, No 1, pp. 113-120, 1983. [CrossRef] [Web of Science Times Cited 175] [8] D. Grant, P. Denyer, I. Finlay, "Synthesis of address generators", In Proc IEEE Int. Conf. Computer Aided Design (ICCAD-89), Santa Clara, CA, 1989, pp. 116-119. [9] H. T. Kung, "Why systolic architectures?", Computer, Vol. 15, No 1, pp. 37-46, January 1982. [CrossRef] [10] V. V. Voevodin, Mathematical models and methods in parallel processing, Nauka, Moscow, 1986 (In Russian). [11] I. Z. Milovanovic, E. I. Milovanovic, M. P. Bekakos, "Synthesis of unidirectional systolic array for matrix-vector multiplication", Math. Comput. Modelling, Vol. 43, No 1-2, pp. 612-619, March 2006. [CrossRef] [Web of Science Times Cited 9] [12] E. I. Milovanovic, M. P. Bekakos, I. Z. Milovanovic, "Synthesis of space optimal systolic arrays for band matrix-vector multiplication", J. Supercomputing, Vol. 49, No 3, pp. 269-290, September 2009. [CrossRef] [Web of Science Times Cited 3] [13] M. P. Bekakos, I. Z. Milovanovic, E. I. Milovanovic, T. I. Tokic, M. K. Stojcev, Hexagonal systolic arrays for matrix multiplication, In: Highly Parallel Computations" Algorithms and Applications (M.P. Bekakos, ed.), Chapter 6, WIT Press, Southampton-Boston, 2001, 139-177. [14] S. G. Sedukhin, "The Designing and Analysis of Systolic Algo- rithms and Structures", Programming, 2, pp. 20-40, 1991, (In Russian.) [15] K. Compton, S. Hauck, "Reconfigurable computing: A syrvey of systems and software", ACM Comput. Surveys, Vol. 34, No 2, pp. 171-210, June 2002. [CrossRef] [Web of Science Times Cited 646] [16] M. Hertz, R. Hartenstein, M. Miranda, E. Brockmeyer, F. Catthoor, "Memory Addressing Organization for Stream-based Reconfigurable Computing", Proc. IEEE ICECS 2002, Dubrovnik, Croatia, 2002, pp. 813-817. [CrossRef] [17] G. Talavera, M. Jayapala, J. Carrabina, F. Catthoor, "Address generation optimization for embedded high-performance Processors: A Survey", J. Sign. Process. Syst., Vol. 53, No 3, pp. 271-284, December 2008. [CrossRef] [Web of Science Times Cited 18] [18] E. I. Milovanovic, T. R. Nikolic, M. K. Stojcev, I. Z. Milovanovic, "Multi-functional systolic array with reconfgurable micro-power processing elements", Microelectron. Reliab., Vol. 49, No 7, pp. 813-820, July 2009. [CrossRef] [Web of Science Times Cited 9] [19] M. K. Stojcev, I. Z. Milovanovic, E. I. Milovanovic, T. R. Nikolic, "Address generators for linear systolic array", Microelectron. Reliab., Vol. 50, No 2, pp. 292-303, February 2010. [CrossRef] [Web of Science Times Cited 4] [20] Embeded Development HW/SW kit, Spartan 3A DSP S3D1800A, MicroBlaze Processor Edition. [21] I. Z. Milovanovic, M. K. Stojcev, E. I. Milovanovic, T. R. Nikolic, "Linear Processor array in DSP", Proc. 28th International Conference on Microelectronics (MIEL 2012), Nis, Serbia, 13-16 May, 2012, pp. 387-392, ISBN 978-1-4673-0236-4 Web of Science® Citations for all references: 918 TCR SCOPUS® Citations for all references: 0 Web of Science® Average Citations per reference: 42 ACR SCOPUS® Average Citations per reference: 0 TCR = Total Citations for References / ACR = Average Citations per Reference We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more Citations for references updated on 2024-04-22 17:16 in 76 seconds. Note1: Web of Science® is a registered trademark of Clarivate Analytics. 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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
