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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  2/2014 - 10

Pipelined Error-detecting Codes in FPGA Testing

BREKHOV, O. See more information about BREKHOV, O. on SCOPUS See more information about BREKHOV, O. on IEEExplore See more information about BREKHOV, O. on Web of Science, RATNIKOV, M. See more information about RATNIKOV, M. on SCOPUS See more information about RATNIKOV, M. on SCOPUS See more information about RATNIKOV, M. on Web of Science
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Download PDF pdficon (933 KB) | Citation | Downloads: 575 | Views: 2,789

Author keywords
field programmable gate arrays, design for testability, automatic testing, cyclic redundancy check codes, error correction codes

References keywords
fpga(13), testing(9), test(7), fpgas(6), fault(6), diagnosis(6), technology(5), design(5), systems(4), science(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-05-31
Volume 14, Issue 2, Year 2014, On page(s): 57 - 62
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.02010
Web of Science Accession Number: 000340868100010
SCOPUS ID: 84901841977

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This article approaches the solution of FPGA testing and research of characteristics at early development stages. The approach offers error-detection code based on universal test firmware. The performed test firmware based on CRC and Hamming codes detect single and multiple faults, and locate fault place (for Hamming code based test firmware).

References | Cited By  «-- Click to see who has cited this paper

[1] B. Pratt, M. Caffrey, P. Graham, K. Morgan, M. Wirthlin, "Improving FPGA Design Robustness with Partial TMR," IRPS 2006.

[2] D. V. Bobrovsky, O.A. Kalashnikov, P.V.Nekrasov, "Functional Control Technique for FPGA Total Ionizing Dose Testing," Proceedings of the Conference RADECS-2012.

[3] R. N. Williams. A Painless Guide to CRC Error Detection Algorithms. Rocksoft Pty Ltd., Australia, 1993.

[4] P. P. Shirvani, E. J. McCluskey, "Fault-Tolerant Systems in a Space Environment: The CRC ARGOS Project," CRC Technical Report No. 98-2 (CSL TR No. 98-774), December 1998, Center For Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, California 94305.

[5] IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language, The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA, 2005.

[6] K. Arshak, E. Jafer, C. Ibala, "Testing FPGA based digital system using XILINX ChipScope logic analyzer," in Electronics Technology. ISSE '06, pp. 355-360, May 10-14, 2006.
[CrossRef] [SCOPUS Times Cited 23]

[7] K. S. Morgan, D. E. Johnson, B. H. Pratt, M. J. Wirthlin, M. P. Caffrey, P. S. Graham, "SEU Induced Error Propagation in FPGAs," in Proceedings of NSREC Conference, Seattle, WA, July 11-15, 2005, Brigham Young University, 459 CB Provo, UT 84602, Los Alamos National Laboratory, Los Alamos, NM 87545.

[8] H. H. Schmit, S. Cadamni, M. Moe, S.C. Goldstein, "Pipeline Reconfigurable FPGAs," Journal of VLSI Signal Processing Systems 24, Kluwer Academic Publishers, pp. 129-146, 2000.
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 12]

[9] M. Abramovici, C. E. Stroud, "BIST-Based Delay-Fault Testing in FPGAs," in Journal of Electronic Testing: Theory and Applications archive, Volume 19 Issue 5, October 2003, pp. 549-558, Kluwer Academic Publishers Norwell, MA, USA
[CrossRef] [Web of Science Times Cited 19] [SCOPUS Times Cited 30]

[10] M. B. Tahoori, "Application-Dependent Diagnosis of FPGAs," in Proceedings of ITC 2004, pp. 645-654, Oct 26-28, 2004,

[11] B. F. Dutton, C. E. Stroud, "Built-In Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs," in Proceedings of 41st Southeastern Symposium on System Theory, pp. 230-234, 2009.
[CrossRef] [Web of Science Times Cited 19] [SCOPUS Times Cited 22]

[12] I. G. Harris, Russell Tessier, "Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures," in ICCAD'00 Proceedings of 2000 IEEE/ACM International Conference on Computer-aided design, pp. 472-476, IEEE Press Piscataway, NJ, USA ©2000.
[CrossRef] [Web of Science Times Cited 19] [SCOPUS Times Cited 25]

[13] M. Latha, M. Senthilmurugan, "Fault Detection and Fault Diagnosis in SRAM-Based FPGA Using BIST," in IRACST - Engineering Science and Technology: An International Journal (ESTIJ), ISSN: 2250-3498, Vol.2, No. 4, August 2012 609

[14] A. Sarvi, C. A. Sharma, R.F. DeMara, "Bist-Based Group Testing for Diagnosis of Embedded FPGA Cores," ESA, pp. 279-283, CSREA Press, 2008.

[15] K. Babulu, M. K. Kumar, "FPGA Realization of Multiple Fault Diagnosis Technique for Faults in SRAM Based FPGAs," in International Journal of Engineering Science and Innovative Technology (IJESIT), Volume 1, Issue 1, September 2012, 48, ISSN: 2319

[16] M. Rozkovec, J. Jenicheck, Z. Pliva, "Using deterministic test vectors to test FPGA circuit," Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 175-180, 2013.

[17] F. Noorbasha, K. Harikishore, Ch. Hemanth, A. Sivasairam, V. Vijaya Raju, "LFSR Test Pattern For Fault Detection and Diagnosis for FPGA CLB Cells," International Journal of Advances in Engineering & Technology, ISSN: 2231-1963, 240, Vol. 3, Issue 1, pp. 240-246, March 2012.

[18] C.-F. Wu, C.-W. Wu, "Testing and Diagnosing Dynamic Reconfigurable FPGA," VLSI Design, Volume 10, Issue 3, pp. 321-333, 2000.

[19] M. G. Gericota , G. R. Alves , M. L. Silva , J. M. Ferreira, "Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing," Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), p.165, July 08-10, 2002
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 14]

[20] Y.-B. Liao, P. Li, A.-W. Ruan, Y.-W. Wang, W.-C. Li, "A HW/SW Co-Verification Technique for FPGA Test," Journal of Electronic Science and Technology of China, Vol. 7, No. 4, 390, December 2009.
[CrossRef] [SCOPUS Times Cited 9]

[21] Y.-C. Chiu, B. Tarun, S. Ye, P.-I Yeh, P.-A. Shen, "The FPGA test system. Project Final Report," Group 5, University of Southern California, December 2010.

References Weight

Web of Science® Citations for all references: 75 TCR
SCOPUS® Citations for all references: 135 TCR

Web of Science® Average Citations per reference: 3 ACR
SCOPUS® Average Citations per reference: 6 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2022-05-11 23:12 in 59 seconds.

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Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

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Faculty of Electrical Engineering and Computer Science
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