Click to open the HelpDesk interface
AECE - Front page banner



JCR Impact Factor: 1.102
JCR 5-Year IF: 0.734
Issues per year: 4
Current issue: Feb 2021
Next issue: May 2021
Avg review time: 55 days


Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


1,618,629 unique visits
Since November 1, 2009

Robots online now


SCImago Journal & Country Rank


Anycast DNS Hosting

 Volume 21 (2021)
     »   Issue 1 / 2021
 Volume 20 (2020)
     »   Issue 4 / 2020
     »   Issue 3 / 2020
     »   Issue 2 / 2020
     »   Issue 1 / 2020
 Volume 19 (2019)
     »   Issue 4 / 2019
     »   Issue 3 / 2019
     »   Issue 2 / 2019
     »   Issue 1 / 2019
 Volume 18 (2018)
     »   Issue 4 / 2018
     »   Issue 3 / 2018
     »   Issue 2 / 2018
     »   Issue 1 / 2018
 Volume 17 (2017)
     »   Issue 4 / 2017
     »   Issue 3 / 2017
     »   Issue 2 / 2017
     »   Issue 1 / 2017
  View all issues  


Release of the v3 version of AECE Journal website. We moved to a new server and implemented the latest cryptographic protocols to assure better compatibility with the most recent browsers. Our website accepts now only TLS 1.2 and TLS 1.3 secure connections.

Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

Starting on the 15th of June 2020 we wiil introduce a new policy for reviewers. Reviewers who provide timely and substantial comments will receive a discount voucher entitling them to an APC reduction. Vouchers (worth of 25 EUR or 50 EUR, depending on the review quality) will be assigned to reviewers after the final decision of the reviewed paper is given. Vouchers issued to specific individuals are not transferable.

Starting on the 15th of December 2019 all paper authors are required to enter their SCOPUS IDs. You may use the free SCOPUS ID lookup form to find yours in case you don't remember it.

Clarivate Analytics published the InCites Journal Citations Report for 2018. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.650, and the JCR 5-Year Impact Factor is 0.639.

Read More »


  1/2016 - 13

Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions

NIMARA, S. See more information about NIMARA, S. on SCOPUS See more information about NIMARA, S. on IEEExplore See more information about NIMARA, S. on Web of Science, AMARICAI, A. See more information about  AMARICAI, A. on SCOPUS See more information about  AMARICAI, A. on SCOPUS See more information about AMARICAI, A. on Web of Science, BONCALO, O. See more information about  BONCALO, O. on SCOPUS See more information about  BONCALO, O. on SCOPUS See more information about BONCALO, O. on Web of Science, POPA, M. See more information about POPA, M. on SCOPUS See more information about POPA, M. on SCOPUS See more information about POPA, M. on Web of Science
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,191 KB) | Citation | Downloads: 490 | Views: 2,044

Author keywords
digital circuits, probabilistic circuits, register transfer level, reliability, simulated fault injection

References keywords
fault(14), test(10), design(10), level(8), circuits(8), injection(7), systems(6), probabilistic(6), vlsi(5), vhdl(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2016-02-28
Volume 16, Issue 1, Year 2016, On page(s): 93 - 98
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.01013
Web of Science Accession Number: 000376995400013
SCOPUS ID: 84960108449

Quick view
Full text preview
This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection (SFI) and the low simulation overhead required by RTL fault injection. The methodology comprises the following steps: the correct simulation of the RTL system, according to a set of input vectors, hierarchical decomposition of the system into basic RTL blocks, logic synthesis of basic RTL blocks, data-dependent SFI for the GL netlists, and RTL SFI. The proposed methodology has been validated in terms of accuracy on a medium sized circuit - the parallel comparator used in Check Node Unit (CNU) of the Low-Density Parity-Check (LDPC) decoders. The methodology has been applied for the reliability analysis of a 128-bit Advanced Encryption Standard (AES) crypto-core, for which the GL simulation was prohibitive in terms of required computational resources.

References | Cited By  «-- Click to see who has cited this paper

[1] P. Korkmaz, B. E. S Akgul, K. Palem "Energy, Performance, and Probability Tradeoffs for Energy-Efficient Probabilistic CMOS Circuits" IEEE Trans. On Circuits and Systems I, vol. 55, Issue 8, 2008,
[CrossRef] [Web of Science Times Cited 26] [SCOPUS Times Cited 42]

[2] B. E. S. Akgul, L. N. Chakrapani, P. Korkmaz, K.V. Palem, "Probabilistic CMOS Technology: A Survey and Future Directions" Proc. 2006 IFIP Int. Conf. on Very Large Scale Integration, 2006, pp. 1-6,
[CrossRef] [SCOPUS Times Cited 32]

[3] K. V. Palem, "Energy aware computing through probabilistic switching: A study of limits", IEEE Trans. on Computers, Vol. 54, Issue 9, 2005, pp. 1123-1137,
[CrossRef] [Web of Science Times Cited 91] [SCOPUS Times Cited 133]

[4] V. De "Near-Threshold Voltage design in nanoscale CMOS", Proc 2013 Design Automation & Test in Europe (DATE), 2013, pp. 612-615,
[CrossRef] [SCOPUS Times Cited 8]

[5] H. Khaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, S. Bokhar "Near Threshold Voltage Design: Opportunities and Challenges" Proc. Design Automation Conference (DAC), 2012, pp. 1153-1158,
[CrossRef] [SCOPUS Times Cited 175]

[6] E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson "Fault Injection into VHDL Models: The MEFISTO Tool", Proc. 24th Annual International Symposium on Fault Tolerant Computing (FTCS-24), 1994, pp 66-75,

[7] J. C. Baraza, J. Gracia, D. Gil, P.J. Gil, "Improvement of Fault Injection Techniques based on VHDL Code Modification", Proc. 10th IEEE International High-Level Design Validation and Test Workshop, 2005, pp. 19-26,
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 38]

[8] J. C. Baraza, J. Gracia, S. Blanc, D. Gil, P.J. Gil "Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code" IEEE Trans. On Very Large Scale Integration (VLSI) Systems, Vol. 16, Issue 6, 2008, pp. 683-706,
[CrossRef] [Web of Science Times Cited 48] [SCOPUS Times Cited 58]

[9] J. Chen, C. Spagnol, S Grandhi, E Popovici, S. Cotofana, A Amaricai "Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits" Proc. 2014 IEEE Annual Symp. On VLSI (ISVLSI), 2014, pp. 380-385,
[CrossRef] [Web of Science Times Cited 1] [SCOPUS Times Cited 13]

[10] M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, et al. "Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis" Proc. 2011 Design Automation and Test in Europe (DATE), 2011, pp. 1-4,

[11] A. Amaricai, S. Nimara, O. Boncalo, J. Chen, E. Popovici "Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits", Proc. 17th Euromicro Digital System Design, 2014, pp. 473-479,
[CrossRef] [Web of Science Times Cited 8] [SCOPUS Times Cited 12]

[12] S. Nimara, A. Amaricai, O. Boncalo, M. Popa "Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects" Proc. 10th Conf. on PhD Research in Microelectronics (PRIME), 2014, pp. 1-4,
[CrossRef] [SCOPUS Times Cited 1]

[13] S. R. Seward, P. K. Lala, "Fault Injection for Verifying Testability at the VHDL Level", Proc. International Test Conference (ITC), 2003,

[14] N. Bombieri, F. Fummi, V. Guarnieri, "Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction", Proc 16th European Test Symposium (ETS), 2011,
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 8]

[15] P. A. Thaker, "Register-Transfer Level Fault Modeling and Test Evaluation Technique for VLSI Circuits", Proc. International Test Conference (ITC), 2000,
[CrossRef] [Web of Science Times Cited 20]

[16] M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, "Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller", Proc 27th IEEE VLSI Test Symposium, 2009,
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 6]

[17] A. Evans, D. Alexandrescu, E. Costenaro, L. Chen "Hierarchical RTL-Based Combinatorial SER Estimation", Proc. 19th Int. On-Line Testing Symp. (IOLTS), 2013, pp. 139-144,
[CrossRef] [SCOPUS Times Cited 18]

[18] M. Sonza Reorda, M. Violante "Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments" Proc. 17th IEEE Symp on Defect and Fault Tolerance in VLSI Systems (DFT), 2002, pp. 263-271,
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 10]

[19] G. B. Hamad, O. Mohamed, Y. Savaria "Probabilistic model checking of single event transient propagation at RTL level" Proc. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014, pp. 471-475,
[CrossRef] [SCOPUS Times Cited 3]

[20] N. Foutris, M. Kaliorakis, S. Tselonis, D. Gizopoulos "Versatile architecture-level fault injection framework for reliability evaluation: A first report" Proc. 20th Int. On-Line Testing Symp. (IOLTS), 2014,
[CrossRef] [SCOPUS Times Cited 10]

[21] M. Weiner, B. Nikolic, Z. Zhang " LDPC Decoder Architecture for High-Data Rate Personal-Area Networks", Proc. Int. Symp on Circuits and Systems (ISCAS), 2011, pp. 1784 - 1787,
[CrossRef] [SCOPUS Times Cited 34]

[22] Y. S. Park, D. Blaauw, D. Sylvester, Z. Zhang, "Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM", IEEE Journal of Solid State Circuits, Vol. 49, Issue 3, 2014, pp. 783-794,
[CrossRef] [Web of Science Times Cited 43] [SCOPUS Times Cited 50]

[23] 128-bit AES crypto-chip Verilog design, [Online] Available: Temporary on-line reference link removed - see the PDF document

[24] D. K. Pradhan Fault-Tolerant Computer System Design, Prentice Hall, 1997

[25] C.-C. Lu, S.-Y. Tseng, "Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter" Proc. IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors (ASAP), 2002, pp. 277-285,
[CrossRef] [Web of Science Times Cited 61] [SCOPUS Times Cited 94]

References Weight

Web of Science® Citations for all references: 339 TCR
SCOPUS® Citations for all references: 745 TCR

Web of Science® Average Citations per reference: 13 ACR
SCOPUS® Average Citations per reference: 29 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2021-05-07 06:43 in 142 seconds.

Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2021
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.

Website loading speed and performance optimization powered by: