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Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling PolicyZAGAN, I. , GAITAN, V. G.
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field programmable gate arrays, pipeline processing, architecture, scheduling, operating systems
architecture(8), time(5), systems(5), real(5), hardware(5)
No common words between the references section and the paper title.
About this article
Date of Publication: 2016-11-30
Volume 16, Issue 4, Year 2016, On page(s): 45 - 50
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2016.04007
Web of Science Accession Number: 000390675900007
SCOPUS ID: 85007570607
A quantitative and qualitative increase in production has been obtained in most fields through the development of CPUs and real-time systems based on them. Such is the case in the industrial sector where the automation process relieved partly or wholly the human activities needed in the manufacturing process. This is mainly due to time sharing in embedded real-time systems and to pseudo-parallel execution of tasks in the implementation of a single central processing unit. The present article presents the validation of the nHSE (Hardware Scheduler Engine) scheduler implemented in hardware by using a FPGA Xilinx Virtex-7, Vivado development platform, and the Vivado Simulator. In this context, our main contribution relates to a custom interrupt management scheduling policy implemented in hardware at the nHSE level, in order to provide predictable execution for asynchronous interrupts. By reducing the jitter when handling with asynchronous interrupts and completely eliminating the uncertainties of the scheduling limit for the set of tasks, a significant improvement of the overall system's predictability has been obtained.
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