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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
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ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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 HIGH-IMPACT PAPER 

A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure

CHIPER, D. F. See more information about CHIPER, D. F. on SCOPUS See more information about CHIPER, D. F. on IEEExplore See more information about CHIPER, D. F. on Web of Science, CRACAN, A. See more information about  CRACAN, A. on SCOPUS See more information about  CRACAN, A. on SCOPUS See more information about CRACAN, A. on Web of Science, BURDIA, D. See more information about BURDIA, D. on SCOPUS See more information about BURDIA, D. on SCOPUS See more information about BURDIA, D. on Web of Science
 
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Download PDF pdficon (1,332 KB) | Citation | Downloads: 1,277 | Views: 944

Author keywords
discrete transforms, digital integrated circuits, field programmable gate arrays, large scale integration, systolic arrays

References keywords
systems(17), circuits(15), processing(14), signal(13), systolic(12), discrete(12), transform(10), efficient(10), algorithm(10), vlsi(9)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-02-28
Volume 17, Issue 1, Year 2017, On page(s): 75 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.01011
Web of Science Accession Number: 000396335900011
SCOPUS ID: 85014197433

Abstract
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In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a new efficient VLSI algorithm based on a regular and modular computational structure called pseudo-band correlation structure. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low hardware complexity and low I/O cost. A highly efficient VLSI chip can be obtained characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N, a good topology with modular, regular and local connections.


References | Cited By  «-- Click to see who has cited this paper

[1] M. Narrroschke, "Coding efficiency of DCT and DST in hybrid video coding," IEEE Journal of Selected Topics in Signal Processing, Vol.7, No.6, pp.1062-1071, 2013.
[CrossRef] [Web of Science Times Cited 7] [SCOPUS Times Cited 9]


[2] F. Kamisli, "Lossless intra coding in HEVC with integer-to-integer DST," 24th European Signal Processing Conference (EUSIPCO 2016), pp. 2440-2444, 2016.
[CrossRef] [SCOPUS Times Cited 2]


[3] E. A. Baran, A. Kuzu, S. Bogosyan, M. Gokasan, A. Sabanovic, "Comparative analysis of a selected DCT-based compression scheme for haptic data transmission," IEEE Transaction on Industrial Informatics, Vol.12, No.3, pp.1146-1155, Dec. 2016.
[CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 14]


[4] G. K. Wallace, "The JPEG still picture compression standard", IEEE Transactions on Consumer Electronics, vol. 32, no.1, pp. 18-34, 1992.
[CrossRef] [Web of Science Times Cited 340] [SCOPUS Times Cited 2103]


[5] M. Kazmi, A. Aziz, P. Akhtar, D.-S. Kundi, "FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations," Advances in Electrical and Computer Engineering, vol.15, no.1, pp.95-104, 2015.
[CrossRef] [Full Text] [Web of Science Times Cited 5] [SCOPUS Times Cited 5]


[6] S. H. Bae, J. Kim, M. Kim, "HEVC-based perceptually adaptive video coding using a DCT-based local distortion detection probability model," IEEE Transaction on Image Processing, Vol.25, No.7, pp.3343-3357, July 2016.
[CrossRef] [Web of Science Times Cited 50] [SCOPUS Times Cited 53]


[7] R. Jia, R. Chen, C. Y. Lin, Z. Guo, H. Yang, "Low cost 1D DCT core for multimedia video codec," Chinese Journal of Electronics, Vol.25, No.6, pp.1052-1057, June 2016,
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 4]


[8] M. Jridi, A. Alfalou, P. K. Meher, "A generalized algorithm and reconfigurable architecture for efficient and scalable orthogonal approximation of DCT," IEEE Transactions on Circuits and Systems I; Regular Papers, Vol.62, No.2, pp.449-457, February 2015.
[CrossRef] [Web of Science Times Cited 57] [SCOPUS Times Cited 64]


[9] J. Nan, N. Yu, W. Lu, D. Wang, "A DST hardware structure of HEVC," 2nd International Conf. on Information Science and Control Engineering, pp.546-549, 2015.
[CrossRef] [Web of Science Record] [SCOPUS Times Cited 5]


[10] C. M. Rader, "Discrete Fourier transform when the number of data samples is prime," Proc. IEEE, vol.56, pp.1107-1108, June 1968.
[CrossRef] [SCOPUS Times Cited 356]


[11] J. I. Guo, C. M. Liu, and C. W. Jen, "A new array architecture for prime-length discrete cosine transform," IEEE Transactions on Signal Processing, vol. SP-41, no.1, pp. 436-442, 1993.
[CrossRef] [SCOPUS Times Cited 52]


[12] J. I. Guo, C. M. Liu, and C. W. Jen, "The efficient memory-based VLSI array design for DFT and DCT," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.39, no.10, pp. 723-733, Oct. 1992.
[CrossRef] [Web of Science Times Cited 56] [SCOPUS Times Cited 80]


[13] D. F. Chiper, "A new systolic array algorithm for memory-based VLSI array implementation of DCT," Proc. Second IEEE Symp. on Computers and Communications, pp.297-301, 1997
[CrossRef] [Web of Science Times Cited 13]


[14] C. Cheng and K. K. Parhi, "Hardware efficient fast DCT based on novel cyclic convolution structures," IEEE Transaction on Signal Processing, vol. 54, no. 11, pp. 4419-4434, Nov. 2006.
[CrossRef] [Web of Science Times Cited 36] [SCOPUS Times Cited 39]


[15] Y. H. Chan and W. C. Siu, "On the realization of discrete cosine transform using the distributed arithmetic," IEEE Transaction on Circuits and Systems I: Fundamental Theory and Applications, vol. 39, no. 9, pp. 705-712, Sept. 1992.
[CrossRef] [Web of Science Times Cited 45] [SCOPUS Times Cited 65]


[16] D. F. Chiper, M. N. S. Swamy, and M. O. Ahmad, "An efficient unified framework for the VLSI implementation of a prime-length DCT/IDCT with high throughput," IEEE Transactions on Signal Processing, Regular Papers, vol.55, no.6, pp. 2925 - 2936, June 2007.
[CrossRef] [Web of Science Times Cited 13] [SCOPUS Times Cited 26]


[17] P. K. Meher, "Systolic designs for DCT using low-complexity concurrent convolutional formulation," IEEE Trans. on Circuits and Systems for Video Technology, vol.16(9), pp.1041-1050, Sept. 2006.
[CrossRef] [Web of Science Times Cited 39] [SCOPUS Times Cited 47]


[18] D. F. Chiper and P. Ungureanu, "Novel VLSI algorithm and architecture with good quantization properties for a high-throughput area efficient systolic array implementation of DCT" EURASIP Journal on Advances in Signal Processing- Special issue on quantization of VLSI digital signal processing systems, Vol. 2011, Jan. 2011.
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 20]


[19] J. Xie, P.K. Meher, J. He, "Hardware-efficient realization of prime-length DCT based on distributed arithmetic," IEEE Transactions on Computers, Vol.62, No.6, pp.1170-1178, June 2013.
[CrossRef] [Web of Science Times Cited 23] [SCOPUS Times Cited 32]


[20] D. F. Chiper, M. N. S. Swamy, M. O. Ahmad, and T. Stouraits, "Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.52, no.6, pp. 1125-1137, June 2005.
[CrossRef] [Web of Science Times Cited 42] [SCOPUS Times Cited 61]


[21] C. H. Chen, B. D. Liu and J. F. Yang, "Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 2017-2030, 2004.
[CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 23]


[22] P. K. Meher and M. N. S. Swamy, "New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 262-266, March 2007.
[CrossRef] [Web of Science Times Cited 25] [SCOPUS Times Cited 34]


[23] I. Protsko, V. Teslyuk, "Computational structure of DST-II using convolvers," The Experience of Designing and Application of CAD System in Microelectronics, pp. 200-202, 2015,
[CrossRef] [SCOPUS Times Cited 1]


[24] D. F. Chiper, M. N. S. Swamy, and M. O. Ahmad, "An efficient systolic array algorithm for the VLSI implementation of a prime-length DHT," in Proc. ISSCS 2005, vol. 1, pp. 167-169, 2005.
[CrossRef] [SCOPUS Times Cited 21]


[25] D. F.Chiper, "A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture," IEEE Transactions on Circuits and Systems-II, vol.60, no.5, pp. 282-286, 2013.
[CrossRef] [Web of Science Times Cited 18] [SCOPUS Times Cited 25]


[26] D. F.Chiper, "Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III," IEEE Transactions on Circuits and Systems-II, vol.59, no.5, pp.297-301, 2012.
[CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 18]


[27] D. F.Chiper, "Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II," IEEE Signal Processing Letters, vol.18, no.11, pp.687-689, 2011.
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 12]


[28] H. Z. Shu, J. S. Wu, C. F. Yang, L. Senhadji, "Fast Radix-3 Algorithm for the Generalized Discrete Hartley Transform of Type II", IEEE Signal Processing Letters., vol. 19, no. 6, pp. 348-351, Jun. 2012.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 6]


[29] L. Jiang, H. Shu, J. Wu, L. Wang and L. Senhadji, "A Novel Split-Radix Fast Algorithm for 2-D Discrete Hartley Transform," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, pp. 911-924, 2010.
[CrossRef] [Web of Science Times Cited 10] [SCOPUS Times Cited 12]


[30] S. A. White, "Applications of distributed arithmetic to digital signal processing: A tutorial review," IEEE ASSP Mag., Vol.6, no.3, pp.4-19, Jul.1989.
[CrossRef] [SCOPUS Times Cited 568]


[31] S. Yu and E. E. Swartzlander, "DCT implementation with distributed arithmetic," IEEE Transaction on Computers, vol. 50, no.9, pp. 985-991, Sept. 2001.
[CrossRef] [Web of Science Times Cited 82] [SCOPUS Times Cited 120]


[32] M. T. Sun, T. C. Chen, and A. M. Gottlieb, "VLSI implementation of a 16 × 16 discrete cosine transform," IEEE Transaction on Circuits and Systems, vol. 36, no. 4, pp. 610-617, Apr. 1989.
[CrossRef] [Web of Science Times Cited 121] [SCOPUS Times Cited 151]


[33] Y. H. Chen, T. Y. Chang and C. Y. Li, "High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 709-714, April 2011.
[CrossRef] [Web of Science Times Cited 19] [SCOPUS Times Cited 29]


[34] J. Xie, P. K. Meher and J. He, "Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic," IEEE Transactions on Computers, vol. 62, no. 6, pp. 1170-1178, June 2013.
[CrossRef] [Web of Science Times Cited 23] [SCOPUS Times Cited 32]


[35] J. I. Guo, C. Chen and C-W. Jen, "Unified array architecture for DCT/DST and their inverses," Electronics Letters, vol. 31, no. 21, pp. 1811-1812, 1995.

[36] H. T. Kung, "Why systolic architectures?," IEEE Computer, vol.15, no.1, pp. 37-46. 1982.
[CrossRef] [SCOPUS Times Cited 1492]


[37] E. I. Milovanovic, M. K. Stojcev, I. Z. Milovanovic, T. R. Nikolic, "Design of Linear Systolic Arrays for Matrix Multiplication," Advances in Electrical and Computer Engineering, vol.14, no.1, pp.37-42, 2014.
[CrossRef] [Full Text] [Web of Science Times Cited 3] [SCOPUS Times Cited 3]


[38] J. V. McCanny, J. G. McWhirter, S. Y. Kung, "The use of data dependence graphs in the design of bit-level systolic arrays", IEEE Trans. Acoustics Speech and Signal Processing, vol. 38, no. 5, pp. 787-793, May 1990.
[CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 24]


[39] C. W. Jen and H. Y. Hsu, "The design of systolic arrays with tags input," Proceedings IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 2263-2266, 7-9 June 1988.
[CrossRef]


[40] J. F. Yang and C. P. Fang, "Compact recursive structures for discrete cosine transform," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 314-321, Apr. 2000.
[CrossRef] [Web of Science Times Cited 21] [SCOPUS Times Cited 27]


[41] W. H. Fang and M. L. Wu, "An efficient unified systolic architecture for the computation of discrete trigonometric transforms," Proc. of IEEE International Symposium on Circuits and Systems, vol. 3, pp. 2092-2095, 1997.
[CrossRef]


[42] W. H. Fang and M. L. Wu, "Unified fully-pipelined implementations of one- and two-dimensional real discrete trigonometric transforms," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E82-A No.10 pp. 2219-2230, Oct. 1999.

[43] S. B. Pan and R. H. Park, "Unified systolic arrays for computation of DCT/DST/DHT," IEEE Transactions on Circuits and Systems for Video Technology, vol. 7, no. 2, pp. 413-419, Apr 1997.
[CrossRef] [SCOPUS Times Cited 57]




References Weight

Web of Science® Citations for all references: 1,139 TCR
SCOPUS® Citations for all references: 5,692 TCR

Web of Science® Average Citations per reference: 26 ACR
SCOPUS® Average Citations per reference: 129 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-11-07 22:09 in 276 seconds.




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