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Stefan cel Mare
University of Suceava
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Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  3/2017 - 10

Enhanced Interrupt Response Time in the nMPRA based on Embedded Real Time Microcontrollers

GAITAN, N. C. See more information about GAITAN, N. C. on SCOPUS See more information about GAITAN, N. C. on IEEExplore See more information about GAITAN, N. C. on Web of Science
 
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Download PDF pdficon (1,677 KB) | Citation | Downloads: 690 | Views: 2,372

Author keywords
architecture, operating systems, registers, scheduling, software

References keywords
hardware(12), systems(8), time(7), architecture(7), real(6), nmpra(6), icstcc(6), control(6), theory(5), scheduler(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2017-08-31
Volume 17, Issue 3, Year 2017, On page(s): 77 - 84
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.03010
Web of Science Accession Number: 000410369500010
SCOPUS ID: 85028523573

Abstract
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In any real-time operating system, task switching and scheduling, interrupts, synchronization and communication between processes, represent major problems. The implementation of these mechanisms through software generates significant delays for many applications. The nMPRA (Multi Pipeline Register Architecture) architecture is designed for the implementation of real-time embedded microcontrollers. It supports the competitive execution of n tasks, enabling very fast switching between them, with a usual delay of one machine cycle and a maximum of 3 machine cycles, for the memory-related work instructions. This is because each task has its own PC (Program Counter), set of pipeline registers and a general registers file. The nMPRA is provided with an advanced distributed interrupt controller that implements the concept of interrupts as threads. This allows the attachment of one or more interrupts to the same task. In this context, the original contribution of this article is to presents the solutions for improving the response time to interrupts when a task has attached a large number of interrupts. The proposed solutions enhance the original architecture for interrupts logic in order to transfer control, to the interrupt handler as soon as possible, and to create an interrupt prioritization at task level.


References | Cited By  «-- Click to see who has cited this paper

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[CrossRef] [Web of Science Times Cited 84] [SCOPUS Times Cited 96]


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[CrossRef] [Web of Science Times Cited 43] [SCOPUS Times Cited 47]


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[CrossRef] [SCOPUS Times Cited 94]


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[CrossRef]


[14] N. C. Gaitan, V. G. Gaitan, E.-E. (Ciobanu) Moisiuc: "Improving Interrupt Handling in the nMPRA", In Development and Application Systems (DAS), 2014 International Conference on. IEEE, pp. 11-15, 15-17 May, 2014.
[CrossRef] [SCOPUS Times Cited 9]


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[16] N. C. Gaitan, I. Zagan, V. G. Gaitan, "Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation," International Journal of Advanced Computer Science and Applications - IJACSA, vol. 6, no. 4, 2015.
[CrossRef]


[17] L. Andries, G. Gaitan, "Dual priority scheduling algorithm used in the nMPRA microcontrollers: Subtitle as needed (paper subtitle)," 2014 18th International Conference on System Theory, Control and Computing (ICSTCC), Sinaia, 2014, pp. 43-47.
[CrossRef] [SCOPUS Times Cited 3]


[18] E. E. C. Moisuc, A. B. Larionescu, I. Ungurean, "Hardware event handling in the hardware real-time operating systems," 2014 18th International Conference on System Theory, Control and Computing (ICSTCC), Sinaia, 2014, pp. 54-58.
[CrossRef] [SCOPUS Times Cited 5]


[19] I. Zagan, V. G. Gaitan, "Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy," Advances in Electrical and Computer Engineering, vol.16, no.4, pp.45-50, 2016,
[CrossRef] [Full Text] [Web of Science Times Cited 7] [SCOPUS Times Cited 6]


[20] E. E. Moisuc, A. B. Larionescu, V. G. Gaitan, "Hardware Event Treating in nMPRA," in 12rt International Conference on Development and Application Systems - DAS, Suceava, Romania, pp. 66-69, 15-17 May, 2014.
[CrossRef] [SCOPUS Times Cited 10]


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[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 1]


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[CrossRef]


[23] L. Andries, V. G. Gaitan, E. E. Moisuc, "Programming paradigm of a microcontroller with hardware scheduler engine and independent pipeline registers - a software approach," 2015 19th International Conference on System Theory, Control and Computing (ICSTCC), Cheile Gradistei, 2015, pp. 705-710.
[CrossRef] [SCOPUS Times Cited 2]


[24] I. Zagan, V. G. Gaitan, "Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy," Advances in Electrical and Computer Engineering, vol.16, no.4, pp.45-50, 2016,
[CrossRef] [Full Text] [Web of Science Times Cited 7] [SCOPUS Times Cited 6]




References Weight

Web of Science® Citations for all references: 396 TCR
SCOPUS® Citations for all references: 674 TCR

Web of Science® Average Citations per reference: 16 ACR
SCOPUS® Average Citations per reference: 27 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-02-21 15:35 in 122 seconds.




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