Click to open the HelpDesk interface
AECE - Front page banner



JCR Impact Factor: 1.221
JCR 5-Year IF: 0.961
SCOPUS CiteScore: 2.5
Issues per year: 4
Current issue: Aug 2021
Next issue: Nov 2021
Avg review time: 88 days


Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


1,776,461 unique visits
Since November 1, 2009

Robots online now


SCImago Journal & Country Rank


Anycast DNS Hosting

 Volume 21 (2021)
     »   Issue 3 / 2021
     »   Issue 2 / 2021
     »   Issue 1 / 2021
 Volume 20 (2020)
     »   Issue 4 / 2020
     »   Issue 3 / 2020
     »   Issue 2 / 2020
     »   Issue 1 / 2020
 Volume 19 (2019)
     »   Issue 4 / 2019
     »   Issue 3 / 2019
     »   Issue 2 / 2019
     »   Issue 1 / 2019
 Volume 18 (2018)
     »   Issue 4 / 2018
     »   Issue 3 / 2018
     »   Issue 2 / 2018
     »   Issue 1 / 2018
 Volume 17 (2017)
     »   Issue 4 / 2017
     »   Issue 3 / 2017
     »   Issue 2 / 2017
     »   Issue 1 / 2017
  View all issues  


Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

SCOPUS published the CiteScore for 2020, computed by using an improved methodology, counting the citations received in 2017-2020 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2020 is 2.5, better than all our previous results.

Release of the v3 version of AECE Journal website. We moved to a new server and implemented the latest cryptographic protocols to assure better compatibility with the most recent browsers. Our website accepts now only TLS 1.2 and TLS 1.3 secure connections.

Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

Starting on the 15th of June 2020 we wiil introduce a new policy for reviewers. Reviewers who provide timely and substantial comments will receive a discount voucher entitling them to an APC reduction. Vouchers (worth of 25 EUR or 50 EUR, depending on the review quality) will be assigned to reviewers after the final decision of the reviewed paper is given. Vouchers issued to specific individuals are not transferable.

Read More »


  2/2018 - 8

Expansible Network-on-Chip Architecture

PIRES, I. L. P. See more information about PIRES, I. L. P. on SCOPUS See more information about PIRES, I. L. P. on IEEExplore See more information about PIRES, I. L. P. on Web of Science, ALVES, M. A. Z. See more information about  ALVES, M. A. Z. on SCOPUS See more information about  ALVES, M. A. Z. on SCOPUS See more information about ALVES, M. A. Z. on Web of Science, ALBINI, L. C. P. See more information about ALBINI, L. C. P. on SCOPUS See more information about ALBINI, L. C. P. on SCOPUS See more information about ALBINI, L. C. P. on Web of Science
View the paper record and citations in View the paper record and citations in Google Scholar
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,347 KB) | Citation | Downloads: 464 | Views: 1,511

Author keywords
computer architecture, multiprocessor interconnection, system-on-chip, reconfigurable architectures, wireless networks

References keywords
chip(11), parallel(9), network(8), architecture(6), systems(5), performance(5), circuits(5), specification(4), multi(4), isscc(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2018-05-31
Volume 18, Issue 2, Year 2018, On page(s): 61 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.02008
Web of Science Accession Number: 000434245000008
SCOPUS ID: 85047879531

Quick view
Full text preview
Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the processing elements. However, the communication outside the chip commonly uses high performance links which have the entire communication protocol stack overhead. This paper introduces the Expansible NoC concept and architecture, which is formed by wired and wireless NoC components in order to provide a low overhead interconnection for intra-chip and inter-chip communication. ENoC couples both networks with the same simplified protocol, enabling the transmission of parallel messages directly in the NoC level. The ability of identifying new communicant on-the-fly increases its flexibility, expanding the system boundaries every time a new system is connected. The ENoC inter-chip wireless link reaches short distances working at 60 GHz with Orthogonal Frequency Division Multiplexing with Quadrature Amplitude Modulation, enabling high bandwidth communication for systems inside a single cluster rack. Experimental evaluations were performed using the Noxim simulator executing computational fluid dynamics benchmark applications. Results show that the proposed architecture improves up to 38% the performance when compared to the newest related work.

References | Cited By  «-- Click to see who has cited this paper

[1] L. Benini and G. D. Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, pp. 70-78, 2002.
[CrossRef] [Web of Science Times Cited 1675] [SCOPUS Times Cited 2885]

[2] S. Deb, A. Ganguly, P. P. Pande, B. Belzer and D. Heo, "Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges," IEEE Journal on Emerging and Selected Topics in Circuits and Systems - (JETCAS), vol. 2, no. 2, pp. 228-239, 2012.
[CrossRef] [Web of Science Times Cited 157] [SCOPUS Times Cited 219]

[3] J. Howard et al., "A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS," in 2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, pp. 108-109.
[CrossRef] [SCOPUS Times Cited 509]

[4] H. C. de Freitas, L. M. Schnorr, M. A. Z. Alves, and P. O. A. Navaux, "Impact of Parallel Workloads on NoC Architecture Design," in 18th Euromicro Conference on Parallel, Distributed and Network-based Processing - (PDP), 2010, pp. 551-555.
[CrossRef] [Web of Science Times Cited 6] [SCOPUS Times Cited 10]

[5] D. Mangano and I. A. Urzi, "System for Designing Network-on-Chip Interconnect Arrangements," US Patent App. 14/940,026, 2016.

[6] B. A. Floyd, C.-M. Hung, and K. K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 543-552, 2002.
[CrossRef] [Web of Science Times Cited 211] [SCOPUS Times Cited 279]

[7] M. F. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher and S. Tam, "CMP Network-on-Chip Overlaid with Multi-band RF-interconnect," in IEEE 14th International Symposium on High Performance Computer Architecture - (HPCA), 2008, pp. 191-202.
[CrossRef] [SCOPUS Times Cited 216]

[8] M. S. Shamim, J. Muralidharan, and A. Ganguly, "An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links," in Proceedings of the 9th International Symposium on Networks-on-Chip - (NOCS), New York, NY, USA, 2015, p. 2:1-2:8.
[CrossRef] [SCOPUS Times Cited 10]

[9] M. S. Shamim, N. Mansoor, R. S. Narde, V. Kothandapani, A. Ganguly, and J. Venkataraman, "A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems," IEEE Transactions on Computers - (TC), vol. 66, no. 3, pp. 389-402, 2017.
[CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 41]

[10] D. DiTomaso, A. Kodi, D. Matolak, S. Kaya, S. Laha, and W. Rayess, "A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors," IEEE Transactions on Parallel and Distributed Systems - (TPDS), vol. 26, no. 12, pp. 3289-3302, 2015.
[CrossRef] [Web of Science Times Cited 32] [SCOPUS Times Cited 43]

[11] WirelessHD Consortium, "WirelessHD Specification Version 1.1 Overview," Specification. California, USA, 2010.

[12] R. C. Daniels, J. N. Murdock, T. S. Rappaport, and R. W. Heath, "60 GHz Wireless: Up Close and Personal," IEEE Microwave Magazine - (MMM), vol. 11, no. 7, pp. 44-50, 2010.
[CrossRef] [Web of Science Times Cited 153] [SCOPUS Times Cited 173]

[13] T. S. Rappaport, Wireless Communications: Principles and Practice. Prentice Hall PTR, 2002.

[14] C. J. Hansen, "WiGiG: Multi-gigabit wireless communications in the 60 GHz band," IEEE Wireless Communications - (MWC), vol. 18, no. 6, pp. 6-7, 2011.
[CrossRef] [Web of Science Times Cited 129] [SCOPUS Times Cited 145]

[15] M. Rohling, T. May, K. Bruninghaus, and R. Grunheid, "Broad-band OFDM radio transmission for multimedia applications," Proceedings of the IEEE, vol. 87, no. 10, pp. 1778-1789, 1999.
[CrossRef] [Web of Science Times Cited 100] [SCOPUS Times Cited 144]

[16] H. Yin and S. Alamouti, "OFDMA: A Broadband Wireless Access Technology," in IEEE Sarnoff Symposium - (SARNOF), 2006, pp. 1-4.
[CrossRef] [SCOPUS Times Cited 96]

[17] D. J. Law, A. Healey, P. Anslow, S. B. Carlson, V. Maguire, and M. Hajduczenia, "IEEE Standard for Ethernet," IEEE Computer Society, Section One, 2015.

[18] WIFI Alliance, "60 GHz Technical Specification," WiFi Alliance, Version 1.0, 2016.

[19] Infiniband TA, "InfiniBand Architecture Specification Volume 1," InfiniBand Trade Association, Release 1.1, 2002.

[20] C. A. Zeferino and A. A. Susin, "SoCIN: a parametric and scalable network-on-chip," in 16th Symposium on Integrated Circuits and Systems Design - (SBCCI), 2003, pp. 169-174.
[CrossRef] [Web of Science Times Cited 94] [SCOPUS Times Cited 162]

[21] M. Frumkin, H. Jin, and J. Yan, "Implementation of NAS Parallel Benchmarks in High Performance Fortran," NASA, 1998.

[22] V. Catania, A. Mineo, S. Monteleone, M. Palesi, and D. Patti, "Noxim: An open, extensible and cycle-accurate network on chip simulator," in IEEE 26th International Conference on Application-specific Systems, Architectures and Processors - (ASAP), 2015, pp. 162-163.
[CrossRef] [SCOPUS Times Cited 381]

[23] R. F. V. der Wijngaart and H. Jin, "NAS Parallel Benchmarks, Multi-Zone Versions," NASA, 2003.

[24] D. Bailey, T. Harris, W. Saphir, R. F. V. der Wijngaart, A. Woo, and M. Yarrow, "The NAS parallel benchmarks 2.0," NASA, 1995.

[25] M. Diener, E. H. M. Cruz, L. L. Pilla, F. Dupros, and P. O. A. Navaux, "Characterizing communication and page usage of parallel applications for thread and data mapping," Journal of Performance Evaluation - (JPEVA), vol. 88, pp. 18-36, 2015.
[CrossRef] [Web of Science Times Cited 27] [SCOPUS Times Cited 38]

[26] H. Krichene, M. Baklouti, P. Marque, J. L. Dekeyser, and M. Abid, "SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC," in 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing - (PDP), 2016, pp. 759-762.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 2]

[27] M. Yuffe, E. Knoll, M. Mehalel, J. Shor, and T. Kurts, "A fully integrated multi-CPU, GPU and memory controller 32nm processor," in 2011 IEEE International Solid-State Circuits Conference - (ISSCC), 2011, pp. 264-266.
[CrossRef] [SCOPUS Times Cited 93]

[28] R. Rajsuman, System-on-a-Chip: Design and Test, 1st ed. Norwood, MA, USA: Artech House, Inc., 2000.

[29] S. Saini et al., "An early performance evaluation of many integrated core architecture based sgi rackable computing system," in International Conference for High Performance Computing, Networking, Storage and Analysis - (SC), 2013, pp. 1-12.
[CrossRef] [Web of Science Times Cited 16] [SCOPUS Times Cited 19]

References Weight

Web of Science® Citations for all references: 2,634 TCR
SCOPUS® Citations for all references: 5,465 TCR

Web of Science® Average Citations per reference: 88 ACR
SCOPUS® Average Citations per reference: 182 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2021-11-26 11:11 in 131 seconds.

Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2021
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.

Website loading speed and performance optimization powered by: