Click to open the HelpDesk interface
AECE - Front page banner



JCR Impact Factor: 1.102
JCR 5-Year IF: 0.734
Issues per year: 4
Current issue: Feb 2021
Next issue: May 2021
Avg review time: 55 days


Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


1,618,613 unique visits
Since November 1, 2009

Robots online now


SCImago Journal & Country Rank


Anycast DNS Hosting

 Volume 21 (2021)
     »   Issue 1 / 2021
 Volume 20 (2020)
     »   Issue 4 / 2020
     »   Issue 3 / 2020
     »   Issue 2 / 2020
     »   Issue 1 / 2020
 Volume 19 (2019)
     »   Issue 4 / 2019
     »   Issue 3 / 2019
     »   Issue 2 / 2019
     »   Issue 1 / 2019
 Volume 18 (2018)
     »   Issue 4 / 2018
     »   Issue 3 / 2018
     »   Issue 2 / 2018
     »   Issue 1 / 2018
 Volume 17 (2017)
     »   Issue 4 / 2017
     »   Issue 3 / 2017
     »   Issue 2 / 2017
     »   Issue 1 / 2017
  View all issues  


Release of the v3 version of AECE Journal website. We moved to a new server and implemented the latest cryptographic protocols to assure better compatibility with the most recent browsers. Our website accepts now only TLS 1.2 and TLS 1.3 secure connections.

Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

Starting on the 15th of June 2020 we wiil introduce a new policy for reviewers. Reviewers who provide timely and substantial comments will receive a discount voucher entitling them to an APC reduction. Vouchers (worth of 25 EUR or 50 EUR, depending on the review quality) will be assigned to reviewers after the final decision of the reviewed paper is given. Vouchers issued to specific individuals are not transferable.

Starting on the 15th of December 2019 all paper authors are required to enter their SCOPUS IDs. You may use the free SCOPUS ID lookup form to find yours in case you don't remember it.

Clarivate Analytics published the InCites Journal Citations Report for 2018. The JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.650, and the JCR 5-Year Impact Factor is 0.639.

Read More »


  3/2019 - 7

Compiler Optimization on Instruction Scheduling for a Specialized Real-Time Floating Point Soft-Core Processor

KIRCHHOFF, M. See more information about KIRCHHOFF, M. on SCOPUS See more information about KIRCHHOFF, M. on IEEExplore See more information about KIRCHHOFF, M. on Web of Science, WAGNER, L. See more information about  WAGNER, L. on SCOPUS See more information about  WAGNER, L. on SCOPUS See more information about WAGNER, L. on Web of Science, FENGLER, W. See more information about FENGLER, W. on SCOPUS See more information about FENGLER, W. on SCOPUS See more information about FENGLER, W. on Web of Science
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (366 KB) | Citation | Downloads: 299 | Views: 1,115

Author keywords
dynamic compiler, optimization methods, processor scheduling, scheduling algorithms, vector processor

References keywords
processor(10), systems(8), design(7), core(7), scheduling(6), fengler(6), embedded(5), compiler(5), time(4), system(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-08-31
Volume 19, Issue 3, Year 2019, On page(s): 57 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.03007
Web of Science Accession Number: 000486574100007
SCOPUS ID: 85072200729

Quick view
Full text preview
This paper presents the authors' research in the field of specialized optimizing assembly language compilers for embedded real-time soft-core processor systems on FPGAs. With this soft-core processor, we are targeting a highly specialized field of applications that require large floating-point precision and other unique characteristics. Therefore, a specialized optimizing assembly language compiler is necessary in order to provide the needed machine code and optimize it in a way that efficient usage of the internal parallelism mechanisms is possible, resulting in major performance benefits on single-core, multi-core and vector processors. One important key feature is the design-time analyzability to meet the hard real-time constraints of any given problem.

References | Cited By  «-- Click to see who has cited this paper

[1] O. Esko, P. Jaaskelainen, P. Huerta, S. Carlos, J. Takala, J. I. Martinez, "Customized exposed datapath soft-core design flow with compiler support", 2010 International Conference on Field Programmable Logic and Applications (FPL), pp. 217-222,
[CrossRef] [SCOPUS Times Cited 63]

[2] Altera Corporation, "Nios II Processor Overview", [Online] Available: Temporary on-line reference link removed - see the PDF document

[3] Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jense, Maxwell Walter, Laust Brock-Nannestad, Lars Bonnichsen, Christian W. Probst, Sven Karlsson, "Automatic generation of application specific FPGA multicore accelerators", Signals Systems and Computers 2014 48th Asilomar Conference on, pp. 1440-1444, 2014,
[CrossRef] [SCOPUS Times Cited 1]

[4] Danko Ivosevic, Vlado Sruk, "Unified flow of custom processor design and FPGA implementation", EUROCON 2013 IEEE, pp. 1721-1727, 2013,
[CrossRef] [SCOPUS Times Cited 4]

[5] Xilinx Inc., "MicroBlaze Soft Processor Core", [Online] Available: Temporary on-line reference link removed - see the PDF document

[6] Gaisler Research, "LEON3 Processor", [Online] Available: Temporary on-line reference link removed - see the PDF document

[7] J. G. Tong, I. D. Anderson, M. A. Khalid, "Soft-core processors for embedded systems", International Conference on Microelectronics, 2006, ICM'06, pp. 170-173,
[CrossRef] [SCOPUS Times Cited 77]

[8] Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, Sven Karlsson, "Hardware realization of an FPGA processor - Operating system call offload and experiences", Design and Architectures for Signal and Image Processing (DASIP) 2014 Conference on, pp. 1-8, 2014,
[CrossRef] [SCOPUS Times Cited 3]

[9] Oliver Stecklina, Michael Methfessel, "A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks", Digital System Design (DSD) 2014 17th Euromicro Conference on, pp. 559-566, 2014,
[CrossRef] [Web of Science Times Cited 3] [SCOPUS Times Cited 4]

[10] M. Kirchhoff, W. Fengler, "Realization of an embedded hard real-time softcore processor", 2014 7th GI Workshop on Autonomous Systems, pp. 33-42.

[11] M. Kirchhoff, N. Kaptsova, D. Streitpferdt, W. Fengler, "Optimizing compiler for a specialized real-time floating point softcore processor", 2017 8th Annual Conference of Industrial Automation and Electromechanical Engineering, IEMECON, pp. 181-188,
[CrossRef] [SCOPUS Times Cited 3]

[12] M. Levy, T. M. Conte, "Embedded multicore processors and systems", IEEE micro, 29(3), pp. 7-9,
[CrossRef] [Web of Science Times Cited 24] [SCOPUS Times Cited 33]

[13] M. W. Hall, J. M. Anderson, S. P. Amarasinghe, B. R. Murphy, S. W. Liao, E. Bugnion, M. S. Lam, "Maximizing multiprocessor performance with the SUIF compiler", Computer, 29(12), pp. 84-89, 1996,
[CrossRef] [Web of Science Times Cited 135] [SCOPUS Times Cited 348]

[14] Jiayin Li, Meikang Qiu, Jianwei Niu, Meiqin Liu, Bin Wang, Jingtong Hu, "Impacts of Inaccurate Information on Resource Allocation for Multi-Core Embedded Systems", Computer and Information Technology (CIT) 2010 IEEE 10th International Conference on, pp. 2692-2697, 2010,
[CrossRef] [SCOPUS Times Cited 4]

[15] Roman Atachiants, Gavin Doherty, David Gregg, "Parallel Performance Problems on Shared-Memory Multicore Systems: Taxonomy and Observation", Software Engineering IEEE Transactions on, vol. 42, no. 8, pp. 764-785, 2016,
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 4]

[16] Sungju Lee, Eunji Lee, Yongwha Chung, Hyeonjoong Cho, Byoungki Min, "Energy-efficient protection of video surveillance data using multicore-based video sensors", Digital Content Multimedia Technology and its Applications (IDC) 2010 6th International Conference on, pp. 327-330, 2010.

[17] E. Sprangle, D. Carmean, "Increasing processor performance by implementing deeper pipelines", ACM SIGARCH Computer Architecture News, Vol. 30, No. 2, pp. 25-34, IEEE Computer Society,
[CrossRef] [Web of Science Times Cited 88]

[18] T. Hagras, J. Janecek. "A high performance, low complexity algorithm for compile-time task scheduling in heterogeneous systems", Parallel Computing, 31(7), pp. 653-670, 2005,

[19] Y. Yan, R. Zheng, "Code Generating Method, Compiler, Scheduling Method, Scheduling Apparatus and Scheduling System", U.S. Patent Application No. 15,058,610, 2016.

[20] G. Diamos, M Mehrara, "Compiler-controlled region scheduling for SIMD execution of threads", U.S. Patent No. 9,424,038. Washington, DC: U.S. Patent and Trademark Office, 2016.

[21] B. Dane, A. Pacholik, S. Zschack, W. Fengler, C. Ament, T. Braune, "Designing a Control Application by Using a Specialized Multi-Core Soft Microprocessor", IFAC Proceedings Volumes, 46(28), pp. 221-226, 2013,
[CrossRef] [SCOPUS Times Cited 1]

[22] S. Novack, A. Nicolau, "Mutation scheduling: A unified approach to compiling for fine-grain parallelism", International Workshop on Languages and Compilers for Parallel Computing, pp. 16-30, Springer Verlag, Berlin, Heidelberg, 1994.

[23] Z. Yu, K. You, R. Xiao, H. Quan, P. Ou, Y. Ying, X. Zeng, "An 800 MHz 320 mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms", 2012 IEEE International Solid-State Circuits Conference, ISSCC, pp. 64-66,
[CrossRef] [SCOPUS Times Cited 26]

[24] S. Dezso, "The design space of register renaming rechniques" 2000 IEEE micro 20 (5), pp. 70-83,
[CrossRef] [Web of Science Times Cited 33] [SCOPUS Times Cited 51]

[25] M. Muller, T. Machleidt, W. Fengler, "SoC Design for Complex Standalone Optical Measurement Devices", 2014 7th GI Workshop on Autonomous Systems, pp. 66-75.

[26] Xilinx Inc., "Zynq-7000 SoC Data Sheet: Overview. DS190 v1.11.1", [Online] Available: Temporary on-line reference link removed - see the PDF document

[27] T. Hausotte, B. Percle, U. Gerhardt, D. Dontsov, E. Manske, G. Jager, "Interference signal demodulation for nanopositioning and nanomeasuring machines", Measurement Science and Technology, 23(7):074004, 2012,
[CrossRef] [Web of Science Times Cited 20] [SCOPUS Times Cited 29]

[28] B. Shenoi, "Introduction to digital signal processing and filter design", John Wiley & Sons, 2005.

[29] A. Pacholik, J. Klockner, M. Muller, I. Gushchina, W. Fengler, "LiSARD: LabVIEW integrated softcore architecture for reconfigurable devices", 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig '11), pp. 442-447, Cancun, Mexico, 2011, IEEE Computer Society CPS,
[CrossRef] [SCOPUS Times Cited 5]

[30] A. Amthor, S. Zschack, C. Ament, "Position control on nanometer scale based on an adaptive friction compensation scheme", 2008 34th Annual Conference of IEEE Industrial Electronics, pp. 2568-2573, IEEE, 2008,
[CrossRef] [SCOPUS Times Cited 12]

[31] S. Zschack, J. Klockner, I. Gushchina, A. Amthor, W. Fengler, "Control of nanopositioning and nanomeasuring machines with a modular FPGA based data processing system", Mechatronics, 23(3):257-263, 2013,
[CrossRef] [Web of Science Times Cited 11] [SCOPUS Times Cited 12]

References Weight

Web of Science® Citations for all references: 316 TCR
SCOPUS® Citations for all references: 680 TCR

Web of Science® Average Citations per reference: 10 ACR
SCOPUS® Average Citations per reference: 21 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2021-05-02 17:51 in 124 seconds.

Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2021
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania

All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.

Website loading speed and performance optimization powered by: