|1/2020 - 13|
Design Time Temperature Reduction in Mixed Polarity Dual Reed-Muller Network: a NSGA-II Based ApproachDAS, A. , PRADHAN, S. N.
|View the paper record and citations in|
|Click to see author's profile in SCOPUS, IEEE Xplore, Web of Science|
|Download PDF (528 KB) | Citation | Downloads: 685 | Views: 1,831|
genetic algorithms, logic design, Pareto optimization, power dissipation, thermal analysis
thermal(7), power(6), aware(6), pradhan(5), circuits(5), systems(4), reed(4), optimization(4), muller(4), design(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2020-02-28
Volume 20, Issue 1, Year 2020, On page(s): 99 - 104
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2020.01013
Web of Science Accession Number: 000518392600013
SCOPUS ID: 85083705344
Proposed work addresses the existing thermal problem of OR-XNOR based circuit by introducing design time thermal management technique at the logic level. The approach is used to reduce the peak temperature by eliminating local hotspots. In proposed thermal-aware synthesis, non-dominated sorting genetic algorithm-II (NSGA-II) based meta-heuristic search algorithm is used to select a suitable input polarity of Mixed Polarity Dual Reed-Muller Expansion (MPDRM) to reduce the power and power-density by optimizing the area sharing. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Finally, the optimized solutions are implemented in the physical design level to obtain the actual values of area, power, and temperature. MCNC benchmark suit is considered for performance evaluation. A comparative study of the proposed approach with existing state-of-art algorithms such as fixed and mixed polarity Reed-Muller network is reported. A significant reduction in area occupancy, power dissipation, and peak temperature generation are reported.
|References|||||Cited By «-- Click to see who has cited this paper|
| L. Shang and R. P. Dick, Thermal crisis: challenges and potential solutions. IEEE Potential, vol. 25, pp. 31-35, 2006. |
[CrossRef] [SCOPUS Times Cited 24]
 A. Das, A. Debnath & S N Pradhan, "Area, power and temperature optimization during binary decision diagram based circuit synthesis," in Proc. IEEE Devices for Integrated Circuit, 2017, pp. 778-782.
[CrossRef] [SCOPUS Times Cited 6]
 A. Iranfar, M. Kamal, A. Afzali-Kusha, M. Pedram & D. Atienza, "Thespot: Thermal stress-aware power and temperature management for multiprocessor systems-on-chip," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 8, pp. 1532-1545, 2018.
[CrossRef] [Web of Science Times Cited 22] [SCOPUS Times Cited 26]
 W. L. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides & M. J. Irwin, "Thermal-aware floorplanning using genetic algorithms," in Proc. IEEE 6th international symposium on quality electronic design (isqed'05), 2005, pp. 634-639.
[CrossRef] [Web of Science Times Cited 54] [SCOPUS Times Cited 93]
 S. H. Gunther, "Managing the impact of increasing microprocessor power consumption," Intel Technology Journal, vol. 5, no. 1, pp. 1-9, 2001.
 A. Das, S. N. Pradhan, "Thermal aware FPRM based AND-XOR network synthesis of logic circuits," in Proc. IEEE 2nd International Conf. on Recent Trends in Information Systems (ReTIS), pp. 497-502, 2015.
[CrossRef] [SCOPUS Times Cited 13]
 A. Das, S. N. Pradhan, "Shared Reed-Muller decision diagram based thermal-aware AND-XOR decomposition of logic circuits," VLSI Design, vol. 2016, pp. 1-14, 2016.
[CrossRef] [SCOPUS Times Cited 13]
 A. Das, S. N. Pradhan, "Area-Power-Temperature Aware AND-XOR Network Synthesis based on Shared Mixed Polarity Reed-Muller Expansion," International Journal of Intelligent Systems and Applications, vol. 10, no. 12, pp. 35-46, 2018.
[CrossRef] [SCOPUS Times Cited 7]
 A. Das, S. N. Pradhan, "Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation," Recent Advances in Electrical & Electronic Engineering, vol. 12, no. 1, pp. 30-39, 2019.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 2]
 N. Alon, T. Kaufman, M. Krivelevich, S. Litsyn, & D. Ron, "Testing reed-muller codes," IEEE Trans. on Inf. Theory, vol. 51, no. 11, pp. 4032-4039, 2005.
[CrossRef] [Web of Science Times Cited 83] [SCOPUS Times Cited 111]
 P. Wang, J. Lu, J. Xu, & J. Dai, "Power optimization algorithm based on XNOR/OR logic," Journal of Electronics, vol. 26, no. 1, pp. 138-144, 2009.
[CrossRef] [SCOPUS Times Cited 2]
 M. Pedram & S. Nazarian, "Thermal modeling, analysis, and management in VLSI circuits: Principles and methods," in Proc. of the IEEE, vol. 94, no. 8, pp. 1487-1501, 2006.
[CrossRef] [Web of Science Times Cited 298] [SCOPUS Times Cited 369]
 M. Yang, L. L. Wang, J. R. Tong & A. E. A. Almaini, "Techniques for dual forms of Reed-Muller expansion conversion," Integration, vol. 41, no. 1, pp. 113-122, 2008.
[CrossRef] [Web of Science Times Cited 9] [SCOPUS Times Cited 14]
 Y. Haizhen, J. Zhidi, W. Pengjun, & L. Kangping, "GA-DTPSO algorithm and its application in area optimization of mixed polarity XNOR/OR circuits," Journal of Computer-Aided Design & Computer Graphics, vol. 27, no. 5, pp. 946-952, 2015.
 K. Deb, A. Pratap, S. Agarwal & T. A. M. T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE trans. on evolutionary computation, vol. 6, no. 2, pp. 182-197, 2002.
[CrossRef] [Web of Science Times Cited 27347] [SCOPUS Times Cited 34243]
 K. Deb, "Multi-objective optimization using evolutionary algorithms," John Wiley and Sons, 2003.
 D. S. H. Ram, M. C. Bhuvaneswari & S. Umadevi, "Improved low power FPGA binding of datapaths from data flow graphs with NSGA II-based schedule selection," Advances in Electrical and Computer Engineering, vol. 13, no. 4, pp. 85-92, 2013.
[CrossRef] [Full Text] [Web of Science Times Cited 4] [SCOPUS Times Cited 4]
 MCNC benchmark suit, [Online] Available: Temporary on-line reference link removed - see the PDF document
 Cadence Innovus implementation system, [Online] Available: Temporary on-line reference link removed - see the PDF document.
 HotSpot, [Online] Available: Temporary on-line reference link removed - see the PDF document
Web of Science® Citations for all references: 27,819 TCR
SCOPUS® Citations for all references: 34,927 TCR
Web of Science® Average Citations per reference: 1,325 ACR
SCOPUS® Average Citations per reference: 1,663 ACR
TCR = Total Citations for References / ACR = Average Citations per Reference
We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more
Citations for references updated on 2023-09-28 20:47 in 88 seconds.
Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.