Click to open the HelpDesk interface
AECE - Front page banner

Menu:


FACTS & FIGURES

JCR Impact Factor: 1.221
JCR 5-Year IF: 0.961
SCOPUS CiteScore: 2.5
Issues per year: 4
Current issue: Aug 2021
Next issue: Nov 2021
Avg review time: 88 days


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


TRAFFIC STATS

1,776,495 unique visits
596,916 downloads
Since November 1, 2009



Robots online now
PetalBot


SJR SCImago RANK

SCImago Journal & Country Rank




TEXT LINKS

Anycast DNS Hosting
MOST RECENT ISSUES

 Volume 21 (2021)
 
     »   Issue 3 / 2021
 
     »   Issue 2 / 2021
 
     »   Issue 1 / 2021
 
 
 Volume 20 (2020)
 
     »   Issue 4 / 2020
 
     »   Issue 3 / 2020
 
     »   Issue 2 / 2020
 
     »   Issue 1 / 2020
 
 
 Volume 19 (2019)
 
     »   Issue 4 / 2019
 
     »   Issue 3 / 2019
 
     »   Issue 2 / 2019
 
     »   Issue 1 / 2019
 
 
 Volume 18 (2018)
 
     »   Issue 4 / 2018
 
     »   Issue 3 / 2018
 
     »   Issue 2 / 2018
 
     »   Issue 1 / 2018
 
 
 Volume 17 (2017)
 
     »   Issue 4 / 2017
 
     »   Issue 3 / 2017
 
     »   Issue 2 / 2017
 
     »   Issue 1 / 2017
 
 
  View all issues  








LATEST NEWS

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

2021-Jun-06
SCOPUS published the CiteScore for 2020, computed by using an improved methodology, counting the citations received in 2017-2020 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2020 is 2.5, better than all our previous results.

2021-Apr-15
Release of the v3 version of AECE Journal website. We moved to a new server and implemented the latest cryptographic protocols to assure better compatibility with the most recent browsers. Our website accepts now only TLS 1.2 and TLS 1.3 secure connections.

2020-Jun-29
Clarivate Analytics published the InCites Journal Citations Report for 2019. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.102 (1.023 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.734.

2020-Jun-11
Starting on the 15th of June 2020 we wiil introduce a new policy for reviewers. Reviewers who provide timely and substantial comments will receive a discount voucher entitling them to an APC reduction. Vouchers (worth of 25 EUR or 50 EUR, depending on the review quality) will be assigned to reviewers after the final decision of the reviewed paper is given. Vouchers issued to specific individuals are not transferable.

Read More »


    
 

  2/2021 - 5

Design, FPGA-based Implementation and Performance of a Pseudo Random Number Generator of Chaotic Sequences

DRIDI, F. See more information about DRIDI, F. on SCOPUS See more information about DRIDI, F. on IEEExplore See more information about DRIDI, F. on Web of Science, EL ASSAD, S. See more information about  EL ASSAD, S. on SCOPUS See more information about  EL ASSAD, S. on SCOPUS See more information about EL ASSAD, S. on Web of Science, EL HADJ YOUSSEF, W. See more information about  EL HADJ YOUSSEF, W. on SCOPUS See more information about  EL HADJ YOUSSEF, W. on SCOPUS See more information about EL HADJ YOUSSEF, W. on Web of Science, MACHHOUT, M. See more information about  MACHHOUT, M. on SCOPUS See more information about  MACHHOUT, M. on SCOPUS See more information about MACHHOUT, M. on Web of Science, SAMHAT, A. E. See more information about SAMHAT, A. E. on SCOPUS See more information about SAMHAT, A. E. on SCOPUS See more information about SAMHAT, A. E. on Web of Science
 
View the paper record and citations in View the paper record and citations in Google Scholar
Click to see author's profile in See more information about the author on SCOPUS SCOPUS, See more information about the author on IEEE Xplore IEEE Xplore, See more information about the author on Web of Science Web of Science

Download PDF pdficon (1,453 KB) | Citation | Downloads: 320 | Views: 319

Author keywords
chaotic, field programmable gate arrays, hardware, performance evaluation, statistical analysis

References keywords
chaotic(10), systems(9), random(8), generation(6), chaos(6), applications(6), implementation(5), design(5), circuits(5), theory(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2021-05-31
Volume 21, Issue 2, Year 2021, On page(s): 41 - 48
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2021.02005
Web of Science Accession Number: 000657126200005
SCOPUS ID: 85107700679

Abstract
Quick view
Full text preview
Pseudo-Random Number Generator of Chaotic Sequences (PRNG-CS) has caught the attention in various security applications, especially for stream and block ciphering, steganography, and digital watermarking algorithms. Indeed, in all chaos-based cryptographic systems, the chaotic generator plays a vital role and exhibits appropriate cryptographic properties. Due to the technological outbreak, as well as the rapid growth of the Internet of Things (IoT) technology and their various use cases, PRNGs-CS software implementation remains an open issue to meet its service requirements. The hardware implementation is one of the most flagship technology used to implement PRNGs-CS with the aim is to provide high-performance requirements for such application security. Therefore, in this work, we propose a new PRNGs-SC-based architecture. The latter consists of three discrete chaotic maps weakly coupled, as well as, the Piecewise Linear Chaotic Map (PWLCM), the Skew Tent, and the Logistic map. The chaotic system is designed on Xilinx Spartan-6 FPGA-board, using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). Simulation results, performed over the ISE Design Suite environment, prove the effectiveness of our proposed architecture in terms of robustness against statistical attacks, throughput, and hardware cost. So, based on its architecture and the simulation results the proposed PRNG-SC can be used in cryptographic applications.


References | Cited By  «-- Click to see who has cited this paper

[1] C. E. Shannon, "Communication theory of secrecy systems," The Bell system technical journal, vol. 28, no. 4, pp. 656-715, 1949.
[CrossRef] [SCOPUS Times Cited 5568]


[2] L. Kocarev, "Chaos-based cryptography: a brief overview," IEEE Circuits and Systems Magazine, vol. 1, no. 3, pp. 6-21, 2001.
[CrossRef] [SCOPUS Times Cited 632]


[3] M. Andrecut, "Logistic map as a random number generator," International Journal of Modern Physics B, vol. 12, no. 09, pp. 921-930, 1998.
[CrossRef] [Web of Science Times Cited 52] [SCOPUS Times Cited 66]


[4] M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli, "Analysis and design of digital PRNGS based on the discretized sawtooth map," in Proc. 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003, IEEE, 2003, pp. 427-430

[5] M. E. Yalcin, J. A. Suykens, J. Vandewalle, "True random bit generation from a double-scroll attractor," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 7, pp. 1395-1404, 2004.
[CrossRef] [Web of Science Times Cited 208] [SCOPUS Times Cited 262]


[6] M. A. Zidan, A. G. Radwan, K. N. Salama, "Random number generation based on digital differential chaos," in Proc. 54th International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE, 2011, pp. 1-4.
[CrossRef] [SCOPUS Times Cited 40]


[7] O. Jallouli, S. El Assad, M. Chetto, R. Lozi, "Design and analysis of two stream ciphers based on chaotic coupling and multiplexing techniques," Multimedia tools and applications, vol. 77, no. 11, pp. 13391-13417, 2018.
[CrossRef] [Web of Science Times Cited 14] [SCOPUS Times Cited 16]


[8] F. Dridi, S. El Assad, W. E. Youssef, M. Machhout, "FPGA Implementation of a pseudo-chaotic number generator and evaluation of its performance," in Proc. 2019 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC), IEEE, 2019, pp. 231-234.
[CrossRef] [SCOPUS Times Cited 3]


[9] G. Gautier, M. Le Glatin, S. El Assad, W. Hamidouche, O. Deforges, S. Guilley, A. Facon, "Hardware implementation of lightweight chaos-based stream cipher", in Proc. The Fourth International Conference on Cyber-Technologies and Cyber-Systems (CYBER 2019), Porto, Portugal, 2019, pp. 37-40

[10] S. El Assad, H. Noura, I. Taralova, "Design and analyses of efficient chaotic generators for crypto-systems," in Proc. Advances in Electrical and Electronics Engineering-IAENG Special Edition of the World Congress on Engineering and Computer Science 2008, IEEE, 2008, pp. 3-12.
[CrossRef] [Web of Science Times Cited 2] [SCOPUS Times Cited 28]


[11] L. Kocarev, G. Jakimoski, "Pseudorandom bits generated by chaotic maps," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 1, pp. 123-126, 2003.
[CrossRef] [Web of Science Times Cited 68] [SCOPUS Times Cited 89]


[12] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The digital tent map: Performance analysis and optimized design as a low-complexity source of pseudorandom bits," IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1451-1458, 2006.
[CrossRef] [Web of Science Times Cited 29] [SCOPUS Times Cited 31]


[13] M. A. -Chenaghlu, M. A. Balafar, M. R. F. -Derakhshi, "A novel image encryption algorithm based on polynomial combination of chaotic maps and dynamic function generation," Signal Processing, vol. 157, pp. 1-13, 2019.
[CrossRef] [Web of Science Times Cited 43] [SCOPUS Times Cited 47]


[14] A. V. Tutueva, E. G. Nepomuceno, A. I. Karimov, V. S. Andreev, D. N. Butusov, "Adaptive chaotic maps and their application to pseudo-random numbers generation," Chaos, Solitons & Fractals, vol. 133, pp. 109615, 2020.
[CrossRef] [Web of Science Times Cited 28] [SCOPUS Times Cited 32]


[15] I. Koyuncu, "Implementation of high speed tangent sigmoid transfer function approximations for artificial neural network applications on FPGA," Advances in Electrical and Computer Engineering, vol. 18, no. 3, pp. 79-86, 2018.
[CrossRef] [Full Text] [Web of Science Times Cited 13] [SCOPUS Times Cited 13]


[16] A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, "A statistical test suite for random and pseudorandom number generators for cryptographic applications," Technical report, Booz-allen and hamilton inc mclean va, 2001.
[CrossRef]


[17] P. F. Verhulst, "Resherches mathematiques sur la loi d'accroissement de la population," Nouveaux memoires de l'academie royale des sciences, vol. 18, pp. 1-41, 1845

[18] S. M. Ulam, "On combination of stochastic and deterministic processes," Bull. Amer. Math. Soc., vol. 53, pp. 1120, 1947

[19] Y. S. Kim, W. W. Zachary, "The physics of phase space: Nonlinear dynamics and chaos, geometric quantization, and wigner function," Springer, vol. 278, 2006

[20] J. L. Valtierra, E. T. Cuautle, Esteban, A. R. Vazquez, "A switched-capacitor skew-tent map implementation for random number generation," International Journal of Circuit Theory and Applications, vol. 45, no. 2, pp. 305-315, 2017.
[CrossRef] [Web of Science Times Cited 31] [SCOPUS Times Cited 38]


[21] Y. Hu, C. Zhu, Z. Wang, "An improved piecewise linear chaotic map based image encryption algorithm," The Scientific World Journal, vol. 2014, 2014.
[CrossRef] [Web of Science Times Cited 4] [SCOPUS Times Cited 24]


[22] E. Barker, L. Feldman, G. Witte, "Recommendation for random number generation using deterministic random bit generators," National Institute of Standards and Technology, 2015.
[CrossRef]


[23] M. Tuna, I. Koyuncu, C. B. Fidan, I. Pehlivan, "Real time implementation of a novel chaotic generator on FPGA," in Proc. 23nd Signal Processing and Communications Applications Conference (SIU). IEEE, 2015, pp. 698-701.
[CrossRef] [SCOPUS Times Cited 10]


[24] H. Guntur, J. Ishii, A. Satoh, "Side-channel attack user reference architecture board SAKURA-G," in Proc. 3rd Global Conference on Consumer Electronics (GCCE), IEEE, 2014, pp. 271-274.
[CrossRef] [SCOPUS Times Cited 35]


[25] M. Tuna, I. Koyuncu, M. Alcin, "Fixed and floating point-based high-speed chaotic oscillator design with different numerical algorithms on FPGA,", 2018.
[CrossRef] [Web of Science Times Cited 24] [SCOPUS Times Cited 26]


[26] K. Pearson, "Contributions to the mathematical theory of evolution," Philosophical Transactions of the Royal Society of London. A, vol. 185, pp. 71-110, 1894.
[CrossRef]


[27] L. Pace, Chi-square tests,. Beginning R. Apress, Berkeley, CA, Springer, pp. 217-228, 2012.
[CrossRef]


[28] D. C. Howell, "Chi-Square Test: Analysis of Contingency Tables," 2011.
[CrossRef]


[29] G. Chen, Y. Mao, C. K. Chui, "A symmetric image encryption scheme based on 3D chaotic cat maps," Chaos, Solitons & Fractals, vol. 21, no. 3, pp. 749-761. 2004.
[CrossRef] [Web of Science Times Cited 1259] [SCOPUS Times Cited 1620]




References Weight

Web of Science® Citations for all references: 1,775 TCR
SCOPUS® Citations for all references: 8,580 TCR

Web of Science® Average Citations per reference: 59 ACR
SCOPUS® Average Citations per reference: 286 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2021-11-24 08:22 in 150 seconds.




Note1: Web of Science® is a registered trademark of Clarivate Analytics.
Note2: SCOPUS® is a registered trademark of Elsevier B.V.
Disclaimer: All queries to the respective databases were made by using the DOI record of every reference (where available). Due to technical problems beyond our control, the information is not always accurate. Please use the CrossRef link to visit the respective publisher site.

Copyright ©2001-2021
Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.

Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.

Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.




Website loading speed and performance optimization powered by: