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Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  3/2021 - 8

Quadrature Signal Generator with Improved DC Offset Compensation

STOJIC, D. See more information about STOJIC, D. on SCOPUS See more information about STOJIC, D. on IEEExplore See more information about STOJIC, D. on Web of Science
 
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Download PDF pdficon (1,859 KB) | Citation | Downloads: 777 | Views: 1,398

Author keywords
estimation, frequency locked loops, nonlinear control systems, phase locked loops, power conversion

References keywords
electronics(19), phase(18), power(16), offset(16), single(8), rejection(6), locked(6), access(6), systems(5), grid(5)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2021-08-31
Volume 21, Issue 3, Year 2021, On page(s): 65 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2021.03008
Web of Science Accession Number: 000691632000008
SCOPUS ID: 85114777511

Abstract
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In this paper a second order generalized integrator (SOGI) based quadrature signal generator (QSG) is proposed with the improved DC offset compensation parameter tuning procedure. Namely, for the conventional DC rejection technique, which comprises an integrator (I) included in the SOGI, the modified parameter tuning procedure is proposed based on the set QSG response damping factor value. In this way, when compared to existing QSG tuning techniques based on empirical trial-and-error approach, simplified parameter tuning procedure is proposed based on proposed parametric equations, which enable improved QSG performance verified by simulation and experimental runs by a single-phase phase-locked loop PLL. In this way the increased SOGI based QSG DC offset compensation speed can be achieved, which is critical in various types of single phase PLL applications.


References | Cited By  «-- Click to see who has cited this paper

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[8] C. Zhang, X. Zhao, X. Wang, X. Chai, Z. Zhang, and X. Guo, "A grid synchronisation PLL method based on mixed second-and third-order generalised integrator for DC-offset elimination and frequency adaptability," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 6, no. 3, pp. 1517-1526, 2018.
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[CrossRef] [SCOPUS Times Cited 29]


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[CrossRef] [Web of Science Times Cited 97] [SCOPUS Times Cited 152]


[14] A. Kulkarni and V. John, "Design of a fast response time single-phase PLL with dc offset rejection capability," Electric Power Systems Research, vol. 145, pp. 35-43, 2017.
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[16] S. Golestan, M. Monfared, F. D. Freijedo, and J. M. Guerrero, "Dynamics assessment of advanced single-phase PLL structures," IEEE Transactions on Industrial Electronics, vol. 60, pp. 2167-2177, 2013.
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[17] Golestan, S., Guerrero, J.M., and Gharehpetian, G.B., "Five approaches to deal with problem of DC offset in phase-locked loop algorithms: Design considerations and performance evaluations", IEEE Transactions on Power Electronics, vol. 31, pp. 648-661, 2016.
[CrossRef] [Web of Science Times Cited 105] [SCOPUS Times Cited 126]


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[20] Ali, Zunaib, Nicholas Christofides, Lenos Hadjidemetriou, and Elias Kyriakides, "Design of an advanced PLL for accurate phase angle extraction under grid voltage HIHs and DC offset," IET Power Electronics, vol. 11, no. 6, pp. 995-1008, 2017.
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[21] Trinh, Quoc Nam, Peng Wang, Yi Tang, Leong Hai Koh, and Fook Hoong Choo, "Compensation of DC offset and scaling errors in voltage and current measurements of three-phase AC/DC converters," IEEE Transactions on Power Electronics, vol. 33, no. 6, pp. 5401-5414, 2017.
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[22] Li, Yunlu, Dazhi Wang, Yi Ning, and Nanmu Hui, "DC-offset elimination method for grid synchronization," Electronics Letters, vol. 53, no. 5, pp. 335-337, 2017.
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[23] Bai, Yu, Xiaoqiang Guo, Baocheng Wang, and Yongjian Li, "Fully digital grid synchronization under harmonics and unbalanced conditions," IEEE Access, no. 7, pp. 109969-109981, 2019.
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[24] Trinh, Quoc Nam, Peng Wang, and Fook Hoong Choo, "An improved control strategy of three-phase PWM rectifiers under input voltage distortions and DC-offset measurement errors," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 5, no. 3, pp. 1164-1176, 2017.
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[25] Kherbachi, Abdelhammid, Aissa Chouder, Ahmed Bendib, Kamel Kara, and Said Barkat, "Enhanced structure of second-order generalized integrator frequency-locked loop suitable for DC-offset rejection in single-phase systems," Electric Power Systems Research, vol. 170, pp. 348-357, 2019.
[CrossRef] [Web of Science Times Cited 44] [SCOPUS Times Cited 51]


[26] S. Preitl and R.-E. Precup, "An extension of tuning relations after Symmetrical Optimum method for PI and PID controllers," Automatica, vol. 35, no. 10, pp. 1731-1736, Oct. 1999.
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[CrossRef] [SCOPUS Times Cited 106]




References Weight

Web of Science® Citations for all references: 2,962 TCR
SCOPUS® Citations for all references: 3,867 TCR

Web of Science® Average Citations per reference: 106 ACR
SCOPUS® Average Citations per reference: 138 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-07-13 14:32 in 182 seconds.




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