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Stefan cel Mare
University of Suceava
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Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  3/2022 - 2

Exploring FPGA Logic Block Architecture for Reduced Configuration Memory

HUSSAIN, F. See more information about HUSSAIN, F. on SCOPUS See more information about HUSSAIN, F. on IEEExplore See more information about HUSSAIN, F. on Web of Science, IQBAL, M. M. See more information about  IQBAL, M. M. on SCOPUS See more information about  IQBAL, M. M. on SCOPUS See more information about IQBAL, M. M. on Web of Science, PARVEZ, H. See more information about  PARVEZ, H. on SCOPUS See more information about  PARVEZ, H. on SCOPUS See more information about PARVEZ, H. on Web of Science, RASHID, M. See more information about RASHID, M. on SCOPUS See more information about RASHID, M. on SCOPUS See more information about RASHID, M. on Web of Science
 
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Download PDF pdficon (1,576 KB) | Citation | Downloads: 335 | Views: 206

Author keywords
clustering algorithms, field programmable gate arrays, programmable logic arrays, reconfigurable architectures, reconfigurable logic

References keywords
fpga(17), systems(12), logic(12), parvez(10), application(10), specific(8), reconfigurable(8), fpgas(8), computing(8), programmable(7)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2022-08-31
Volume 22, Issue 3, Year 2022, On page(s): 15 - 24
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2022.03002
Web of Science Accession Number: 000861021000002
SCOPUS ID: 85137679653

Abstract
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The reduction of reconfiguration delay, during the partial dynamic reconfiguration of FPGAs, is important. In this context, the bitstream compression technique is one of the widely used techniques. These compression techniques only minimize the size of the bitstream whereas the actual configuration memory size on FPGA remains the same, which consumes area as well as power. Therefore, alternative techniques are required to decrease area and power consumption along with the reconfiguration delays. This work optimizes the configuration memory requirements in the Configurable Logic Block (CLB) of FPGA with SRAM table sharing technique. The SRAM table of a Look-Up-Table (LUT) is shared with one or more LUTs in the same CLB by employing Negation-Permutation-Negation (NPN) classification. Furthermore, the relevant CAD tools are modified to explore the heterogeneous degree of SRAM table sharing within a CLB. For validation, extensive explorations are performed on the 20 largest MCNC benchmark circuits. It has been found that the configuration memory requirements of LUTs are reduced by 30% while retaining the same area, occupancy, and delay. Moreover, it can be further reduced by 50% provided that the FPGA occupancy is allowed to increase by only 15% while retaining the same delay.


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References Weight

Web of Science® Citations for all references: 1,395 TCR
SCOPUS® Citations for all references: 2,562 TCR

Web of Science® Average Citations per reference: 39 ACR
SCOPUS® Average Citations per reference: 71 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2022-11-26 06:04 in 324 seconds.




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