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Stefan cel Mare
University of Suceava
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Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  1/2024 - 8

Efficient and Power-Aware Design of a Novel Sparse Kogge-Stone Adder using Hybrid Carry Prefix Generator Adder

KHAN, A. See more information about KHAN, A. on SCOPUS See more information about KHAN, A. on IEEExplore See more information about KHAN, A. on Web of Science, WAIRYA, S. See more information about WAIRYA, S. on SCOPUS See more information about WAIRYA, S. on SCOPUS See more information about WAIRYA, S. on Web of Science
 
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Download PDF pdficon (1,721 KB) | Citation | Downloads: 340 | Views: 285

Author keywords
circuit simulation, circuit topology, digital circuits, parallel architectures, very large scale integration

References keywords
adder(20), systems(12), carry(12), high(11), design(11), adders(11), speed(9), circuits(8), prefix(7), parallel(7)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2024-02-29
Volume 24, Issue 1, Year 2024, On page(s): 71 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2024.01008
SCOPUS ID: 85189442408

Abstract
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This paper presents a novel Sparse Kogge-Stone adder architecture with a sparsity factor of 2, offering a compelling solution to the challenges faced by parallel prefix adders. The superior performance is achieved by including the hybrid carry prefix generator adder (HCPGA), which leads to the elimination of redundant components, and improvements in power consumption and circuit area without compromising computation speed. The proposed hybrid architecture efficiently generates carry prefixes that negates the need for the conventional generate and propagate block, resulting in reduced computational complexity. The effectiveness of the proposed architecture has been extensively validated using Cadence Virtuoso in the 45nm technology node. In addition to evaluating standard performance parameters such as power, delay, and area, comprehensive Monte Carlo simulations and process corner analyses have been performed to ensure the robustness and reliability of the design. Furthermore, the practical application of the proposed architecture has been demonstrated by integrating it into a digital multiplier architecture, showcasing its potential to enhance the computational capabilities of complex arithmetic circuits. This research contributes to the advancement of efficient adder designs for high-performance computing applications, making it highly beneficial and relevant for modern digital circuit designs.


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References Weight

Web of Science® Citations for all references: 516 TCR
SCOPUS® Citations for all references: 954 TCR

Web of Science® Average Citations per reference: 14 ACR
SCOPUS® Average Citations per reference: 25 ACR

TCR = Total Citations for References / ACR = Average Citations per Reference

We introduced in 2010 - for the first time in scientific publishing, the term "References Weight", as a quantitative indication of the quality ... Read more

Citations for references updated on 2024-05-25 10:44 in 222 seconds.




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