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Improving Multicore Architectures by Selective Value Prediction of High-Latency Arithmetic InstructionsBUDULECI, C. , GELLERT, A. , FLOREA, A. , BRAD, R. |
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Author keywords
multicore processing, computer simulation, prediction methods, benchmark testing, microprocessors
References keywords
prediction(22), gellert(12), architecture(10), vintan(8), comput(8), florea(7), sibiu(6), selective(6), microarchitecture(6), micro(6)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2024-05-31
Volume 24, Issue 2, Year 2024, On page(s): 61 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2024.02007
Web of Science Accession Number: 001242091800007
SCOPUS ID: 85191685636
Abstract
This work is an original contribution consisting in the implementation and evaluation of a selective value predictor in a multicore environment, with focus on long latency arithmetical instructions, having the goal to break the dataflow bottleneck of each core, thus increasing the overall performance. The Sniper simulator was used to augment the Intel Nehalem architecture with a value predictor and to estimate the computing performance, area of integration, power consumption, energy efficiency and chip temperature for the enhanced architecture. We run simulations and study the impact of the number of values which are used for prediction for each instruction. By increasing the history length, we measured on average more than 3 % increase in performance (core speed-up), a reduction in chip temperature from 57.8 C to 56.17 C, and lower energy consumption in most cases compared with the baseline configuration. We also realized a comparison between the value prediction and dynamic instruction reuse techniques in equitable condition (to exploit the same value locality), where we highlight the advantages and disadvantages of each technique in the given context. |
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