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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
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13, Universitatii Street
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ROMANIA

Print ISSN: 1582-7445
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WorldCat: 643243560
doi: 10.4316/AECE


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  2/2013 - 1
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Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)

CUEVAS-FARFAN, E. See more information about CUEVAS-FARFAN, E. on SCOPUS See more information about CUEVAS-FARFAN, E. on IEEExplore See more information about CUEVAS-FARFAN, E. on Web of Science, MORALES-SANDOVAL, M. See more information about  MORALES-SANDOVAL, M. on SCOPUS See more information about  MORALES-SANDOVAL, M. on SCOPUS See more information about MORALES-SANDOVAL, M. on Web of Science, MORALES-REYES, A. See more information about  MORALES-REYES, A. on SCOPUS See more information about  MORALES-REYES, A. on SCOPUS See more information about MORALES-REYES, A. on Web of Science, FEREGRINO-URIBE, C. See more information about  FEREGRINO-URIBE, C. on SCOPUS See more information about  FEREGRINO-URIBE, C. on SCOPUS See more information about FEREGRINO-URIBE, C. on Web of Science, ALGREDO-BADILLO, I. See more information about  ALGREDO-BADILLO, I. on SCOPUS See more information about  ALGREDO-BADILLO, I. on SCOPUS See more information about ALGREDO-BADILLO, I. on Web of Science, KITSOS, P. See more information about  KITSOS, P. on SCOPUS See more information about  KITSOS, P. on SCOPUS See more information about KITSOS, P. on Web of Science, CUMPLIDO, R. See more information about CUMPLIDO, R. on SCOPUS See more information about CUMPLIDO, R. on SCOPUS See more information about CUMPLIDO, R. on Web of Science
 
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Download PDF pdficon (1,421 KB) | Citation | Downloads: 2,339 | Views: 1,770

Author keywords
data security, cryptography, public key, algorithm design and analysis, field programmable gate arrays

References keywords
karatsuba(12), systems(6), reconfigurable(6), ofman(6), efficient(6), multipliers(5), multiplication(5), reduction(4), parallel(4), multiplier(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2013-05-31
Volume 13, Issue 2, Year 2013, On page(s): 3 - 10
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2013.02001
Web of Science Accession Number: 000322179400001
SCOPUS ID: 84878919037

Abstract
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In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.


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Cited-By CrossRef

[1] High performance AES-GCM implementation based on efficient AES and FR-KOA multiplier, Zhang, Yong, Wu, Ning, Zhou, Fang, Zhang, Xiaoqiang, Zhang, Jinbao, IEICE Electronics Express, ISSN 1349-2543, Issue 14, Volume 15, 2018.
Digital Object Identifier: 10.1587/elex.15.20180559
[CrossRef]

[2] High-performance optimization of SM4-GCM based on FPGA, Lv, Shun Sen, Li, Bin, Chen, Xiaojie, Zhou, Qinglei, 2021 International Conference on Advanced Computing and Endogenous Security, ISBN 978-1-6654-2449-3, 2022.
Digital Object Identifier: 10.1109/IEEECONF52377.2022.10013330
[CrossRef]

[3] Design of N-Term Scalable High-Performance Modular Multiplication Operator on GF (2m), Zhang, Benjun, Wu, Ning, Zhou, Fang, Ge, Fen, Fei, Caixian, 2021 IEEE 4th International Conference on Electronics Technology (ICET), ISBN 978-1-7281-7673-4, 2021.
Digital Object Identifier: 10.1109/ICET51757.2021.9451142
[CrossRef]

[4] An Area-Efficient SM2 Cryptographic Engine for WBAN Security Enhancement, Pei, Hongzhe, Wang, Gang, He, Guanghui, 2023 6th International Conference on Electronics Technology (ICET), ISBN 979-8-3503-3769-3, 2023.
Digital Object Identifier: 10.1109/ICET58434.2023.10212039
[CrossRef]

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