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Enhanced Interrupt Response Time in the nMPRA based on Embedded Real Time MicrocontrollersGAITAN, N. C.   |
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Author keywords
architecture, operating systems, registers, scheduling, software
References keywords
hardware(12), systems(8), time(7), architecture(7), real(6), nmpra(6), icstcc(6), control(6), theory(5), scheduler(5)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2017-08-31
Volume 17, Issue 3, Year 2017, On page(s): 77 - 84
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2017.03010
Web of Science Accession Number: 000410369500010
SCOPUS ID: 85028523573
Abstract
In any real-time operating system, task switching and scheduling, interrupts, synchronization and communication between processes, represent major problems. The implementation of these mechanisms through software generates significant delays for many applications. The nMPRA (Multi Pipeline Register Architecture) architecture is designed for the implementation of real-time embedded microcontrollers. It supports the competitive execution of n tasks, enabling very fast switching between them, with a usual delay of one machine cycle and a maximum of 3 machine cycles, for the memory-related work instructions. This is because each task has its own PC (Program Counter), set of pipeline registers and a general registers file. The nMPRA is provided with an advanced distributed interrupt controller that implements the concept of interrupts as threads. This allows the attachment of one or more interrupts to the same task. In this context, the original contribution of this article is to presents the solutions for improving the response time to interrupts when a task has attached a large number of interrupts. The proposed solutions enhance the original architecture for interrupts logic in order to transfer control, to the interrupt handler as soon as possible, and to create an interrupt prioritization at task level. |
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[1] An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications, Găitan, Vasile Gheorghiță, Zagan, Ionel, Sensors, ISSN 1424-8220, Issue 13, Volume 21, 2021.
Digital Object Identifier: 10.3390/s21134500 [CrossRef]
[2] CPU Execution Time Analysis based on RISC-V ISA Simulators: A Survey, Iuga, Nicolai, Zagan, Ionel, Gaitan, Vasile Gheorghita, 2022 International Conference on Development and Application Systems (DAS), ISBN 978-1-6654-8162-5, 2022.
Digital Object Identifier: 10.1109/DAS54948.2022.9786163 [CrossRef]
Updated 2 days, 19 hours ago
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
