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The Events Priority in the nMPRA and Consumption of Resources Analysis on the FPGACIOBANU, E.-E.   |
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Author keywords
architecture, operating systems, pipeline registers, interrupts, hardware scheduler
References keywords
hardware(9), architecture(9), nmpra(6), time(5), systems(5), system(5), research(5), implementation(5), technology(4), scheduling(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2018-02-28
Volume 18, Issue 1, Year 2018, On page(s): 137 - 144
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.01017
Web of Science Accession Number: 000426449500017
SCOPUS ID: 85043233566
Abstract
The MPRA (Multi Pipeline Register Architecture) was modified and converted into n-task MPRA (nMPRA) by replicating the pipeline registers. While the original MPRA provided hardware scheduling, the interrupts and the events caused too long delays. The author proposes the original solutions for the interrupts and the events treatment, which represent the author's contribution to improving nMPRA; after the theoretical presentations of these solutions in the author's previous articles, this paper presents the implementations of the schemes, the results of the tests and the improved schemes. The MPRA, MPRA4 and MPRA8 implementations on FPGA (Field Programmable Gate Array) were used to evaluate performances. A detailed analysis, partially presented in this paper, shows other advantages: no extra software is required, the hardware implementation is simple, the interrupts and events are similarly handled and the tasks synchronizations and communications are completely based on hardware; MPRA has a low power consumption, even multiplied by eight times, it is reasonably necessary memory and logic resource consumption multiplied by about four times at MPRA4 (compared to MPRA) and by about eight times at MPRA8. |
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[1] Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation, Zagan, Ionel, Găitan, Vasile Gheorghiţă, PeerJ Computer Science, ISSN 2376-5992, Issue , 2023.
Digital Object Identifier: 10.7717/peerj-cs.1300 [CrossRef]
[2] Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded Systems, ZAGAN, I., TANASE, C. A., GAITAN, V. G., Advances in Electrical and Computer Engineering, ISSN 1582-7445, Issue 1, Volume 20, 2020.
Digital Object Identifier: 10.4316/AECE.2020.01009 [CrossRef] [Full text]
[3] FPGA implementation of hardware accelerated RTOS based on real-time event handling, Zagan, Ionel, Găitan, Vasile Gheorghiță, The Journal of Supercomputing, ISSN 0920-8542, Issue 11, Volume 79, 2023.
Digital Object Identifier: 10.1007/s11227-023-05151-0 [CrossRef]
[4] Designing a Custom CPU Architecture Based on Hardware RTOS and Dynamic Preemptive Scheduler, Zagan, Ionel, Găitan, Vasile Gheorghiță, Mathematics, ISSN 2227-7390, Issue 15, Volume 10, 2022.
Digital Object Identifier: 10.3390/math10152637 [CrossRef]
[5] Synthesis analysis and evaluation of hardware scheduler based on different scheduling algorithms, Zagan, Ionel, 2018 International Conference on Development and Application Systems (DAS), ISBN 978-1-5386-1493-8, 2018.
Digital Object Identifier: 10.1109/DAAS.2018.8396064 [CrossRef]
[6] Hardware Scheduler Implementation based on Replicated Resource Architecture for Reconfigurable Systems, Zagan, Ionel, Găitan, Vasile Gheorghiţă, Proceedings of the 2019 3rd International Symposium on Computer Science and Intelligent Control, ISBN 9781450376617, 2019.
Digital Object Identifier: 10.1145/3386164.3386175 [CrossRef]
[7] Improving the performance of Real-Time Event Processing based on Preemptive Scheduler FPGA Implementation, Zagan, Ionel, Gaitan, Vasile Gheorghita, 2020 International Conference on Development and Application Systems (DAS), ISBN 978-1-7281-6870-8, 2020.
Digital Object Identifier: 10.1109/DAS49615.2020.9108930 [CrossRef]
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Stefan cel Mare University of Suceava, Romania
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
