3/2015 - 2 |
Instruction-level Real-time Secure Processor Using an Error Correction CodeYOON, S. M. , LEE, S. W. , PARK, J. K. , KIM, J. T. |
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Author keywords
secure processor, security, instruction, correlation, chain
References keywords
security(5), systems(4), secure(4), execution(4), efficient(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2015-08-31
Volume 15, Issue 3, Year 2015, On page(s): 13 - 16
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2015.03002
Web of Science Accession Number: 000360171500002
SCOPUS ID: 84940746882
Abstract
In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area. |
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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