2/2010 - 3 |
New Techniques for Implementation of Hardware Algorithms inside FPGA CircuitsIOAN, A. D. |
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Author keywords
algorithm organigram, execution section, sequencer, transition matrix, user interface
References keywords
fpga(7), design(7), link(5), xilinx(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2010-05-31
Volume 10, Issue 2, Year 2010, On page(s): 16 - 23
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2010.02003
Web of Science Accession Number: 000280312600003
SCOPUS ID: 77954626692
Abstract
This work presents a less known theoretical method for the synthesis of complex hardware automata by using the transition matrix, together with a new practical method for visual implementation inside FPGA circuits, with library schematic symbols from the Altium Designer software environment. Because these techniques need to be presented by example, the classical shift and add unsigned multiply algorithm was chosen for review. Obviously, this is not the most efficient algorithm, but it serves the declared purpose and it can still be used in a real system when the hardware must be minimal. Furthermore, an essential correction to the optimal version of this algorithm was made. The techniques are exemplified by doing an original implementation: starting from the initial organigram, passing through transition matrix synthesis stage and reaching to the final fully functional system on a Digilent Spartan-3 FPGA development board, which includes the user interface too. |
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[1] Coarse Grained ADRES Based MIMO-OFDM Transceiver with New Radix- $${2}^{5}$$ 2 5 Pipeline FFT/IFFT Processor, Janakiraman, N., Nirmalkumar, P., Akram, Syed Mohsin, Circuits, Systems, and Signal Processing, ISSN 0278-081X, Issue 3, Volume 34, 2015.
Digital Object Identifier: 10.1007/s00034-014-9880-8 [CrossRef]
[2] FPGA Implementation of BLDC Motor Driver with Hall Sensor Feedback, Mihalache, George, Ioan, Aleodor-Daniel, 2018 International Conference and Exposition on Electrical And Power Engineering (EPE), ISBN 978-1-5386-5062-2, 2018.
Digital Object Identifier: 10.1109/ICEPE.2018.8559886 [CrossRef]
[3] Designing an optimal single chip FPGA video interface for embedded systems, Ioan, Aleodor Daniel, 2010 3rd International Symposium on Electrical and Electronics Engineering (ISEEE), ISBN 978-1-4244-8406-5, 2010.
Digital Object Identifier: 10.1109/ISEEE.2010.5628542 [CrossRef]
[4] FPGA implementation of a matrix structure for integer division, Alecsa, Bogdan Claudiu, Ioan, Aleodor Daniel, 2010 3rd International Symposium on Electrical and Electronics Engineering (ISEEE), ISBN 978-1-4244-8406-5, 2010.
Digital Object Identifier: 10.1109/ISEEE.2010.5628505 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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