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JCR Impact Factor: 0.700
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SCOPUS CiteScore: 1.8
Issues per year: 4
Current issue: Nov 2024
Next issue: Feb 2025
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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2024-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2023. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.700 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.600.

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

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  3/2019 - 3

HPOFS: A High Performance and Secured OpenFlow Switch Architecture for FPGA

PHAM-QUOC, C. See more information about PHAM-QUOC, C. on SCOPUS See more information about PHAM-QUOC, C. on IEEExplore See more information about PHAM-QUOC, C. on Web of Science, NGO, D.-M. See more information about  NGO, D.-M. on SCOPUS See more information about  NGO, D.-M. on SCOPUS See more information about NGO, D.-M. on Web of Science, THINH, T. N. See more information about THINH, T. N. on SCOPUS See more information about THINH, T. N. on SCOPUS See more information about THINH, T. N. on Web of Science
 
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Download PDF pdficon (687 KB) | Citation | Downloads: 1,140 | Views: 1,350

Author keywords
field programmable gate arrays, software defined networking, computer security, high performance computing, reconfigurable architectures

References keywords
networks(12), link(12), software(10), defined(10), security(9), openflow(9), network(8), networking(7), communications(7), ddos(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2019-08-31
Volume 19, Issue 3, Year 2019, On page(s): 19 - 28
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2019.03003
Web of Science Accession Number: 000486574100003
SCOPUS ID: 85072163116

Abstract
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Although Software Defined Networking offers many advantages, it suffers from many security issues due to centralized control. In this paper, we introduce HPOFS (High-Performance and Secured OpenFlow Switching Architecture) for FPGA which is not only able to route packets from sources to destinations according to the OpenFlow protocol but also able to protect the system against different attacks efficiently. Thanks to FPGA technology, the two processes can be scheduled in parallel; thus, the switch can work at very high throughput. We implement the first prototype version on Xilinx xc5vtx240t FPGA device with three different security functions to protect the system against DDoS attack types, including Hop-count filtering, port Ingress/Egress filtering, and SYN Flood attacks defender. While the first two protection techniques are adapted from our previous work, the SYN Flood defender core is designed and implemented with a pipeline model in this work. The core is able to protect the system against SYN Flood attacks at up to 30,000,000 packets per second with only 0.248 ms overhead. The full switch can provide throughput at up to 78.96 Gbps with only 0.0012 percent drop rate.


References | Cited By

Cited-By Clarivate Web of Science

Web of Science® Times Cited: 2 [View]
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Cited-By SCOPUS

SCOPUS® Times Cited: 2
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Cited-By CrossRef

[1] Heterogeneous Hardware-based Network Intrusion Detection System with Multiple Approaches for SDN, Ngo, Duc-Minh, Pham-Quoc, Cuong, Thinh, Tran Ngoc, Mobile Networks and Applications, ISSN 1383-469X, Issue 3, Volume 25, 2020.
Digital Object Identifier: 10.1007/s11036-019-01437-x
[CrossRef]

[2] A comprehensive survey of DDoS defense solutions in SDN: Taxonomy, research challenges, and future directions, Kaur, Sukhveer, Kumar, Krishan, Aggarwal, Naveen, Singh, Gurdeep, Computers & Security, ISSN 0167-4048, Issue , 2021.
Digital Object Identifier: 10.1016/j.cose.2021.102423
[CrossRef]

Updated 2 days, 14 hours ago

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