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PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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Clarivate Analytics published the InCites Journal Citations Report for 2023. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.700 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.600.

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Design of Linear Systolic Arrays for Matrix Multiplication

MILOVANOVIC, E. I. See more information about MILOVANOVIC, E. I. on SCOPUS See more information about MILOVANOVIC, E. I. on IEEExplore See more information about MILOVANOVIC, E. I. on Web of Science, STOJCEV, M. K. See more information about  STOJCEV, M. K. on SCOPUS See more information about  STOJCEV, M. K. on SCOPUS See more information about STOJCEV, M. K. on Web of Science, MILOVANOVIC, I. Z. See more information about  MILOVANOVIC, I. Z. on SCOPUS See more information about  MILOVANOVIC, I. Z. on SCOPUS See more information about MILOVANOVIC, I. Z. on Web of Science, NIKOLIC, T. R. See more information about NIKOLIC, T. R. on SCOPUS See more information about NIKOLIC, T. R. on SCOPUS See more information about NIKOLIC, T. R. on Web of Science
 
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Download PDF pdficon (753 KB) | Citation | Downloads: 2,084 | Views: 6,236

Author keywords
address generator units, linear systolic arrays, matrix multiplication

References keywords
milovanovic(14), systolic(9), matrix(9), reconfigurable(5), multiplication(5), stojcev(4), processing(4), bekakos(4), arrays(4), array(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-02-28
Volume 14, Issue 1, Year 2014, On page(s): 37 - 42
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.01006
Web of Science Accession Number: 000332062300006
SCOPUS ID: 84894636997

Abstract
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This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs.


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Cited-By CrossRef

[1] Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication, Waris, Haroon, Wang, Chenghua, Liu, Weiqiang, Lombardi, Fabrizio, 2019 IEEE International Workshop on Signal Processing Systems (SiPS), ISBN 978-1-7281-1927-4, 2019.
Digital Object Identifier: 10.1109/SiPS47522.2019.9020404
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