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JCR Impact Factor: 0.700
JCR 5-Year IF: 0.700
SCOPUS CiteScore: 1.8
Issues per year: 4
Current issue: Aug 2024
Next issue: Nov 2024
Avg review time: 56 days
Avg accept to publ: 60 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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2024-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2023. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.700 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.600.

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

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  2/2024 - 7

Improving Multicore Architectures by Selective Value Prediction of High-Latency Arithmetic Instructions

BUDULECI, C. See more information about BUDULECI, C. on SCOPUS See more information about BUDULECI, C. on IEEExplore See more information about BUDULECI, C. on Web of Science, GELLERT, A. See more information about  GELLERT, A. on SCOPUS See more information about  GELLERT, A. on SCOPUS See more information about GELLERT, A. on Web of Science, FLOREA, A. See more information about  FLOREA, A. on SCOPUS See more information about  FLOREA, A. on SCOPUS See more information about FLOREA, A. on Web of Science, BRAD, R. See more information about BRAD, R. on SCOPUS See more information about BRAD, R. on SCOPUS See more information about BRAD, R. on Web of Science
 
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Download PDF pdficon (1,450 KB) | Citation | Downloads: 450 | Views: 492

Author keywords
multicore processing, computer simulation, prediction methods, benchmark testing, microprocessors

References keywords
prediction(22), gellert(12), architecture(10), vintan(8), comput(8), florea(7), sibiu(6), selective(6), microarchitecture(6), micro(6)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2024-05-31
Volume 24, Issue 2, Year 2024, On page(s): 61 - 72
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2024.02007
Web of Science Accession Number: 001242091800007
SCOPUS ID: 85191685636

Abstract
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This work is an original contribution consisting in the implementation and evaluation of a selective value predictor in a multicore environment, with focus on long latency arithmetical instructions, having the goal to break the dataflow bottleneck of each core, thus increasing the overall performance. The Sniper simulator was used to augment the Intel Nehalem architecture with a value predictor and to estimate the computing performance, area of integration, power consumption, energy efficiency and chip temperature for the enhanced architecture. We run simulations and study the impact of the number of values which are used for prediction for each instruction. By increasing the history length, we measured on average more than 3 % increase in performance (core speed-up), a reduction in chip temperature from 57.8 C to 56.17 C, and lower energy consumption in most cases compared with the baseline configuration. We also realized a comparison between the value prediction and dynamic instruction reuse techniques in equitable condition (to exploit the same value locality), where we highlight the advantages and disadvantages of each technique in the given context.


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Cited-By CrossRef

[1] Architectural and Technological Approaches for Efficient Energy Management in Multicore Processors, Buduleci, Claudiu, Gellert, Arpad, Florea, Adrian, Brad, Remus, Computers, ISSN 2073-431X, Issue 4, Volume 13, 2024.
Digital Object Identifier: 10.3390/computers13040084
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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