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JCR Impact Factor: 0.700
JCR 5-Year IF: 0.700
SCOPUS CiteScore: 1.8
Issues per year: 4
Current issue: Aug 2024
Next issue: Nov 2024
Avg review time: 56 days
Avg accept to publ: 60 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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A Proposed Signal Reconstruction Algorithm over Bandlimited Channels for Wireless Communications, ASHOUR, A., KHALAF, A., HUSSEIN, A., HAMED, H., RAMADAN, A.
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LATEST NEWS

2024-Jun-20
Clarivate Analytics published the InCites Journal Citations Report for 2023. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.700 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.600.

2023-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2022. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.800 (0.700 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 1.000.

2023-Jun-05
SCOPUS published the CiteScore for 2022, computed by using an improved methodology, counting the citations received in 2019-2022 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2022 is 2.0. For "General Computer Science" we rank #134/233 and for "Electrical and Electronic Engineering" we rank #478/738.

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering for 2021 is 2.5, the same as for 2020 but better than all our previous results.

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  1/2024 - 8

Efficient and Power-Aware Design of a Novel Sparse Kogge-Stone Adder using Hybrid Carry Prefix Generator Adder

KHAN, A. See more information about KHAN, A. on SCOPUS See more information about KHAN, A. on IEEExplore See more information about KHAN, A. on Web of Science, WAIRYA, S. See more information about WAIRYA, S. on SCOPUS See more information about WAIRYA, S. on SCOPUS See more information about WAIRYA, S. on Web of Science
 
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Download PDF pdficon (1,721 KB) | Citation | Downloads: 759 | Views: 955

Author keywords
circuit simulation, circuit topology, digital circuits, parallel architectures, very large scale integration

References keywords
adder(20), systems(12), carry(12), high(11), design(11), adders(11), speed(9), circuits(8), prefix(7), parallel(7)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2024-02-29
Volume 24, Issue 1, Year 2024, On page(s): 71 - 80
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2024.01008
Web of Science Accession Number: 001178765900007
SCOPUS ID: 85189442408

Abstract
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This paper presents a novel Sparse Kogge-Stone adder architecture with a sparsity factor of 2, offering a compelling solution to the challenges faced by parallel prefix adders. The superior performance is achieved by including the hybrid carry prefix generator adder (HCPGA), which leads to the elimination of redundant components, and improvements in power consumption and circuit area without compromising computation speed. The proposed hybrid architecture efficiently generates carry prefixes that negates the need for the conventional generate and propagate block, resulting in reduced computational complexity. The effectiveness of the proposed architecture has been extensively validated using Cadence Virtuoso in the 45nm technology node. In addition to evaluating standard performance parameters such as power, delay, and area, comprehensive Monte Carlo simulations and process corner analyses have been performed to ensure the robustness and reliability of the design. Furthermore, the practical application of the proposed architecture has been demonstrated by integrating it into a digital multiplier architecture, showcasing its potential to enhance the computational capabilities of complex arithmetic circuits. This research contributes to the advancement of efficient adder designs for high-performance computing applications, making it highly beneficial and relevant for modern digital circuit designs.


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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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