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Expansible Network-on-Chip ArchitecturePIRES, I. L. P.   , ALVES, M. A. Z. , ALBINI, L. C. P. |
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Author keywords
computer architecture, multiprocessor interconnection, system-on-chip, reconfigurable architectures, wireless networks
References keywords
chip(11), parallel(9), network(8), architecture(6), systems(5), performance(5), circuits(5), specification(4), multi(4), isscc(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2018-05-31
Volume 18, Issue 2, Year 2018, On page(s): 61 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2018.02008
Web of Science Accession Number: 000434245000008
SCOPUS ID: 85047879531
Abstract
Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the processing elements. However, the communication outside the chip commonly uses high performance links which have the entire communication protocol stack overhead. This paper introduces the Expansible NoC concept and architecture, which is formed by wired and wireless NoC components in order to provide a low overhead interconnection for intra-chip and inter-chip communication. ENoC couples both networks with the same simplified protocol, enabling the transmission of parallel messages directly in the NoC level. The ability of identifying new communicant on-the-fly increases its flexibility, expanding the system boundaries every time a new system is connected. The ENoC inter-chip wireless link reaches short distances working at 60 GHz with Orthogonal Frequency Division Multiplexing with Quadrature Amplitude Modulation, enabling high bandwidth communication for systems inside a single cluster rack. Experimental evaluations were performed using the Noxim simulator executing computational fluid dynamics benchmark applications. Results show that the proposed architecture improves up to 38% the performance when compared to the newest related work. |
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[2] Scalable THz Network-On-Chip Architecture for Multichip Systems, Tahanian, Esmaeel, Tajary, Alireza, Rezvani, Mohsen, Fateh, Mansoor, Suseendran, G., Journal of Computer Networks and Communications, ISSN 2090-715X, Issue , 2020.
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[4] A Novel Wireless Network-on-Chip Architecture for Multicore Systems, Tahanian, Esmaeel, Rezvani, Mohsen, Fateh, Mansoor, 2021 26th International Computer Conference, Computer Society of Iran (CSICC), ISBN 978-1-6654-1241-4, 2021.
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
