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Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded SystemsZAGAN, I.   , TANASE, C. A. , GAITAN, V. G. |
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Author keywords
pipeline processing, field programmable gate arrays, architecture, operating systems, scheduling
References keywords
systems(8), architecture(7), hardware(6), risc(5), time(4), processor(4), fpga(4), electronics(4)
Blue keywords are present in both the references section and the paper title.
About this article
Date of Publication: 2020-02-28
Volume 20, Issue 1, Year 2020, On page(s): 63 - 70
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2020.01009
Web of Science Accession Number: 000518392600009
SCOPUS ID: 85083742572
Abstract
Task context switching, unitary management of events, synchronization and communication mechanisms are significant problems for each real-time operating system. For real-time systems, another overhead factor is the processor's time to execute the routine of treating external asynchronous interrupts. The main objective of this paper is to describe, implement, and validate the preemptive scheduler module as part of the hardware accelerated real-time operating system, using the RISC-V instruction set and Verilog HDL. The new architecture contains the hardware structure used for static and dynamic scheduling of the tasks, real-time management of the events, and also defines a method used to attach interrupts to tasks. In order to accomplish this objective, it was necessary to structure CPU modules so as to ensure easy adaptation to other implementations (MIPS coprocessor, ARM or RISC-V). |
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[1] An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications, Găitan, Vasile Gheorghiță, Zagan, Ionel, Sensors, ISSN 1424-8220, Issue 13, Volume 21, 2021.
Digital Object Identifier: 10.3390/s21134500 [CrossRef]
[2] AFTAB: A RISC-V Implementation with Configurable Gateways for Security, Rajabalipanah, Maryam, Roodsari, Mahboobe Sadeghipour, Jahanpeima, Zahra, Roascio, Gianluca, Prinetto, Paolo, Navabi, Zainalabedin, 2021 IEEE East-West Design & Test Symposium (EWDTS), ISBN 978-1-6654-4503-0, 2021.
Digital Object Identifier: 10.1109/EWDTS52692.2021.9580979 [CrossRef]
[3] ENEST - Efficient Interrupt Nesting for RISC-V based CPUs, Lindgren, Per, Dzialo, Pawel, Lunnikivi, Henri, Ericsson, Johan, 2023 IEEE 2nd Industrial Electronics Society Annual On-Line Conference (ONCON), ISBN 979-8-3503-5797-4, 2023.
Digital Object Identifier: 10.1109/ONCON60463.2023.10431132 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
All rights reserved: Advances in Electrical and Computer Engineering is a registered trademark of the Stefan cel Mare University of Suceava. No part of this publication may be reproduced, stored in a retrieval system, photocopied, recorded or archived, without the written permission from the Editor. When authors submit their papers for publication, they agree that the copyright for their article be transferred to the Faculty of Electrical Engineering and Computer Science, Stefan cel Mare University of Suceava, Romania, if and only if the articles are accepted for publication. The copyright covers the exclusive rights to reproduce and distribute the article, including reprints and translations.
Permission for other use: The copyright owner's consent does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific written permission must be obtained from the Editor for such copying. Direct linking to files hosted on this website is strictly prohibited.
Disclaimer: Whilst every effort is made by the publishers and editorial board to see that no inaccurate or misleading data, opinions or statements appear in this journal, they wish to make it clear that all information and opinions formulated in the articles, as well as linguistic accuracy, are the sole responsibility of the author.
