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Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGASKLYAROV, V. , SKLIAROVA, I.
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hamming weight counter, hamming weight comparator, field-programmable gate array, digital signal processing slice, hardware accelerator, on-chip architecture
link(10), hamming(6), circuits(6), systems(5), skliarova(5), sklyarov(4), parallel(4), fpga(4), digital(4)
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About this article
Date of Publication: 2014-05-31
Volume 14, Issue 2, Year 2014, On page(s): 63 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.02011
Web of Science Accession Number: 000340868100011
SCOPUS ID: 84901843912
This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP) slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL) specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations). Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.
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 In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array, Cheng, Long, Li, Jiancong, Zheng, Hao‐Xuan, Yuan, Peng, Yin, Jiahao, Yang, Ling, Luo, Qing, Li, Yi, Lv, Hangbing, Chang, Ting‐Chang, Miao, Xiangshui, Advanced Electronic Materials, ISSN 2199-160X, Issue 9, Volume 6, 2020.
Digital Object Identifier: 10.1002/aelm.202000457 [CrossRef]
 Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs, Pilz, Sarah, Porrmann, Florian, Kaiser, Martin, Hagemeyer, Jens, Hogan, James M., Rückert, Ulrich, Algorithms, ISSN 1999-4893, Issue 2, Volume 13, 2020.
Digital Object Identifier: 10.3390/a13020047 [CrossRef]
 Accelerating Population Count with a Hardware Co-Processor for MicroBlaze, Skliarova, Iouliia, Journal of Low Power Electronics and Applications, ISSN 2079-9268, Issue 2, Volume 11, 2021.
Digital Object Identifier: 10.3390/jlpea11020020 [CrossRef]
 On-chip hardware accelerators for data processing and combinatorial search, Sklyarov, Valery, Skliarova, Iouliia, 2015 9th International Conference on Application of Information and Communication Technologies (AICT), ISBN 978-1-4673-6855-1, 2015.
Digital Object Identifier: 10.1109/ICAICT.2015.7338515 [CrossRef]
 Programmable systems-on-chip for information processing, Sklyarov, Valery, Skliarova, Iouliia, 2014 IEEE 8th International Conference on Application of Information and Communication Technologies (AICT), ISBN 978-1-4799-4119-3, 2014.
Digital Object Identifier: 10.1109/ICAICT.2014.7035967 [CrossRef]
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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania
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