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Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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  2/2014 - 11

 HIGH-IMPACT PAPER 

Hamming Weight Counters and Comparators based on Embedded DSP Blocks for Implementation in FPGA

SKLYAROV, V. See more information about SKLYAROV, V. on SCOPUS See more information about SKLYAROV, V. on IEEExplore See more information about SKLYAROV, V. on Web of Science, SKLIAROVA, I. See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on SCOPUS See more information about SKLIAROVA, I. on Web of Science
 
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Download PDF pdficon (1,071 KB) | Citation | Downloads: 2,104 | Views: 2,247

Author keywords
hamming weight counter, hamming weight comparator, field-programmable gate array, digital signal processing slice, hardware accelerator, on-chip architecture

References keywords
link(10), hamming(6), circuits(6), systems(5), skliarova(5), sklyarov(4), parallel(4), fpga(4), digital(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2014-05-31
Volume 14, Issue 2, Year 2014, On page(s): 63 - 68
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2014.02011
Web of Science Accession Number: 000340868100011
SCOPUS ID: 84901843912

Abstract
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This paper is dedicated to the design, implementation and evaluation of fast FPGA-based circuits that compute Hamming weights for binary vectors and compare the results with fixed thresholds and variable bounds. It is shown that digital signal processing (DSP) slices that are widely available in contemporary FPGAs may be used efficiently and they frequently provide the fastest and least resource consuming solutions. A thorough analysis and comparison of these with the best known alternatives both in hardware and in software is presented. The results are supported by numerous experiments in recent prototyping boards. A fully synthesizable hardware description language (VHDL) specification for one of the proposed core components is given that is ready to be synthesized, implemented, tested and compared in any FPGA that contains embedded DSP48E1 slices (or alternatively DSP48A1 slices from previous generations). Finally, the results of comparisons are provided that include discussions of designs in an ARM processor combined with reconfigurable logic for very long vectors.


References | Cited By

Cited-By Clarivate Web of Science

Web of Science® Times Cited: 7 [View]
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Cited-By SCOPUS

SCOPUS® Times Cited: 8
View record in SCOPUS®
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View citations in SCOPUS® [Free preview]

Updated 6 days, 9 hours ago

Cited-By CrossRef

[1] Tapped delay line for compact time-to-digital converter on UltraScale FPGA and its coding method, Zhu, Min, Qi, Xihan, Cui, Tang, Gao, Qiang, Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, Issue , 2023.
Digital Object Identifier: 10.1016/j.nima.2023.168639
[CrossRef]

[2] In‐Memory Hamming Weight Calculation in a 1T1R Memristive Array, Cheng, Long, Li, Jiancong, Zheng, Hao‐Xuan, Yuan, Peng, Yin, Jiahao, Yang, Ling, Luo, Qing, Li, Yi, Lv, Hangbing, Chang, Ting‐Chang, Miao, Xiangshui, Advanced Electronic Materials, ISSN 2199-160X, Issue 9, Volume 6, 2020.
Digital Object Identifier: 10.1002/aelm.202000457
[CrossRef]

[3] Accelerating Binary String Comparisons with a Scalable, Streaming-Based System Architecture Based on FPGAs, Pilz, Sarah, Porrmann, Florian, Kaiser, Martin, Hagemeyer, Jens, Hogan, James M., Rückert, Ulrich, Algorithms, ISSN 1999-4893, Issue 2, Volume 13, 2020.
Digital Object Identifier: 10.3390/a13020047
[CrossRef]

[4] Accelerating Population Count with a Hardware Co-Processor for MicroBlaze, Skliarova, Iouliia, Journal of Low Power Electronics and Applications, ISSN 2079-9268, Issue 2, Volume 11, 2021.
Digital Object Identifier: 10.3390/jlpea11020020
[CrossRef]

[5] On-chip hardware accelerators for data processing and combinatorial search, Sklyarov, Valery, Skliarova, Iouliia, 2015 9th International Conference on Application of Information and Communication Technologies (AICT), ISBN 978-1-4673-6855-1, 2015.
Digital Object Identifier: 10.1109/ICAICT.2015.7338515
[CrossRef]

[6] A proposal of FH-SS synchronization with FPGA multichannel correlator implementation, Trifunovic, Milan, Malcic, Boris, Sajic, Slavko, 2022 XIV International Symposium on Industrial Electronics and Applications (INDEL), ISBN 978-1-6654-7187-9, 2022.
Digital Object Identifier: 10.1109/INDEL55690.2022.9965506
[CrossRef]

[7] Programmable systems-on-chip for information processing, Sklyarov, Valery, Skliarova, Iouliia, 2014 IEEE 8th International Conference on Application of Information and Communication Technologies (AICT), ISBN 978-1-4799-4119-3, 2014.
Digital Object Identifier: 10.1109/ICAICT.2014.7035967
[CrossRef]

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