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JCR Impact Factor: 0.825
JCR 5-Year IF: 0.752
SCOPUS CiteScore: 2.5
Issues per year: 4
Current issue: Aug 2022
Next issue: Nov 2022
Avg review time: 74 days
Avg accept to publ: 48 days
APC: 300 EUR


PUBLISHER

Stefan cel Mare
University of Suceava
Faculty of Electrical Engineering and
Computer Science
13, Universitatii Street
Suceava - 720229
ROMANIA

Print ISSN: 1582-7445
Online ISSN: 1844-7600
WorldCat: 643243560
doi: 10.4316/AECE


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LATEST NEWS

2022-Jun-28
Clarivate Analytics published the InCites Journal Citations Report for 2021. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 0.825 (0.722 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.752.

2022-Jun-16
SCOPUS published the CiteScore for 2021, computed by using an improved methodology, counting the citations received in 2018-2021 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2021 is 2.5, the same as for 2020 but better than all our previous results.

2021-Jun-30
Clarivate Analytics published the InCites Journal Citations Report for 2020. The InCites JCR Impact Factor of Advances in Electrical and Computer Engineering is 1.221 (1.053 without Journal self-cites), and the InCites JCR 5-Year Impact Factor is 0.961.

2021-Jun-06
SCOPUS published the CiteScore for 2020, computed by using an improved methodology, counting the citations received in 2017-2020 and dividing the sum by the number of papers published in the same time frame. The CiteScore of Advances in Electrical and Computer Engineering in 2020 is 2.5, better than all our previous results.

2021-Apr-15
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  1/2020 - 9

Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded Systems

ZAGAN, I. See more information about ZAGAN, I. on SCOPUS See more information about ZAGAN, I. on IEEExplore See more information about ZAGAN, I. on Web of Science, TANASE, C. A. See more information about  TANASE, C. A. on SCOPUS See more information about  TANASE, C. A. on SCOPUS See more information about TANASE, C. A. on Web of Science, GAITAN, V. G. See more information about GAITAN, V. G. on SCOPUS See more information about GAITAN, V. G. on SCOPUS See more information about GAITAN, V. G. on Web of Science
 
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Download PDF pdficon (989 KB) | Citation | Downloads: 588 | Views: 1,201

Author keywords
pipeline processing, field programmable gate arrays, architecture, operating systems, scheduling

References keywords
systems(8), architecture(7), hardware(6), risc(5), time(4), processor(4), fpga(4), electronics(4)
Blue keywords are present in both the references section and the paper title.

About this article
Date of Publication: 2020-02-28
Volume 20, Issue 1, Year 2020, On page(s): 63 - 70
ISSN: 1582-7445, e-ISSN: 1844-7600
Digital Object Identifier: 10.4316/AECE.2020.01009
Web of Science Accession Number: 000518392600009
SCOPUS ID: 85083742572

Abstract
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Task context switching, unitary management of events, synchronization and communication mechanisms are significant problems for each real-time operating system. For real-time systems, another overhead factor is the processor's time to execute the routine of treating external asynchronous interrupts. The main objective of this paper is to describe, implement, and validate the preemptive scheduler module as part of the hardware accelerated real-time operating system, using the RISC-V instruction set and Verilog HDL. The new architecture contains the hardware structure used for static and dynamic scheduling of the tasks, real-time management of the events, and also defines a method used to attach interrupts to tasks. In order to accomplish this objective, it was necessary to structure CPU modules so as to ensure easy adaptation to other implementations (MIPS coprocessor, ARM or RISC-V).


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Cited-By CrossRef

[1] An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications, Găitan, Vasile Gheorghiță, Zagan, Ionel, Sensors, ISSN 1424-8220, Issue 13, Volume 21, 2021.
Digital Object Identifier: 10.3390/s21134500
[CrossRef]

[2] AFTAB: A RISC-V Implementation with Configurable Gateways for Security, Rajabalipanah, Maryam, Roodsari, Mahboobe Sadeghipour, Jahanpeima, Zahra, Roascio, Gianluca, Prinetto, Paolo, Navabi, Zainalabedin, 2021 IEEE East-West Design & Test Symposium (EWDTS), ISBN 978-1-6654-4503-0, 2021.
Digital Object Identifier: 10.1109/EWDTS52692.2021.9580979
[CrossRef]

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Faculty of Electrical Engineering and Computer Science
Stefan cel Mare University of Suceava, Romania


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